Abstract: A method includes forming a first and a second contact opening to reveal a first and a second source/drain region, respectively, forming a mask layer having a first and a second portion in the first and the second contact openings, respectively, forming a first and a second sacrificial ILD in the first and the second contact openings, respectively, removing the first sacrificial ILD from the first contact opening, filling a filler in the first contact opening, and etching the second sacrificial ILD. The filler protects the first portion of the mask layer from being etched. An ILD is formed in the second contact opening and on the second portion of the mask layer. The filler and the first portion of the mask layer are removed using a wet etch to reveal the first contact opening. A contact plug is formed in the first contact opening.

Abstract: A method includes forming a transistor including forming a source/drain region on a side of a dummy gate stack, forming a first Inter-Layer Dielectric (ILD) covering the source/drain region, and replacing the dummy gate stack with a replacement gate stack. The method further includes forming a second ILD over the first ILD and the replacement gate stack, and forming a lower source/drain contact plug electrically coupling to the source/drain region. The lower source/drain contact plug penetrates through both the first ILD and the second ILD. A third ILD is formed over the second ILD. A gate contact plug is formed in the second ILD and the third ILD. An upper source/drain contact plug is formed overlapping and contacting the lower source/drain contact plug. The upper source/drain contact plug penetrates through the third ILD. The upper source/drain contact plug and the gate contact plug are formed of different materials.

Abstract: A method includes providing a device structure having an isolation structure, a fin adjacent the isolation structure and taller than the isolation structure, and gate structures over the fin and the isolation structure. The isolation structure, the fin, and the gate structures define a first trench over the fin and a second trench over the isolation structure. The method further includes forming a first contact etch stop layer (CESL) over the gate structures, the fin, and the isolation structure; depositing a first inter-layer dielectric (ILD) layer over the first CESL and filling in the first and second trenches; and recessing the first ILD layer such that the first ILD layer in the first trench is removed and the first ILD layer in the second trench is recessed to a level that is about even with a top surface of the fin.

Abstract: A method includes providing a device structure having an isolation structure, a fin adjacent the isolation structure and taller than the isolation structure, and gate structures over the fin and the isolation structure. The isolation structure, the fin, and the gate structures define a first trench over the fin and a second trench over the isolation structure. The method further includes forming a first contact etch stop layer (CESL) over the gate structures, the fin, and the isolation structure; depositing a first inter-layer dielectric (ILD) layer over the first CESL and filling in the first and second trenches; and recessing the first ILD layer such that the first ILD layer in the first trench is removed and the first ILD layer in the second trench is recessed to a level that is about even with a top surface of the fin.

Abstract: A method includes providing a structure that includes a substrate; first and second gate structures over the substrate; first and second source/drain (S/D) features over the substrate; a first dielectric layer over sidewalls of the first and second gate structures and the first and second S/D features; and a second dielectric layer over the first dielectric layer. The first and second S/D features are adjacent to the first and second gate structures respectively. The first and second S/D features comprise different materials. The method further includes etching the first and second dielectric layers to expose the first and second S/D features; doping a p-type dopant to the first and second S/D features; and performing a selective etching process to the first and second S/D features after the doping of the p-type dopant. The selective etching process recesses the first S/D feature faster than it recesses the second S/D feature.

Abstract: A semiconductor device includes: an isolation insulating layer; fin structures protruding from the isolation insulating layer; gate structures, each having a metal gate and a cap insulating layer disposed over the metal gate; a first source/drain epitaxial layer and a second source/drain epitaxial layer disposed between two adjacent gate structures; and a first conductive contact disposed on the first source/drain epitaxial layer, and a second conductive contact disposed on the second source/drain epitaxial layer; a separation isolation region disposed between the first and second conductive contact; and an insulating layer disposed between the separation isolation region and the isolation insulating layer. The separation isolation region is made of a different material than the insulating layer.

Abstract: A method for semiconductor fabrication includes providing a device structure having an isolation structure, a fin adjacent the isolation structure, gate structures over the fin and the isolation structure, one or more dielectric layers over the isolation structure and the fin and between the gate structures, a first contact hole over the fin, and a second contact hole over the isolation structure. The method further includes depositing a protection layer and treating it with a plasma so that the protection layer in the first contact hole and the protection layer in the second contact hole have different etch selectivity in an etching process; and etching the protection layer to etch through the protection layer on the bottom surface of the first contact hole without etching through the protection layer on the bottom surface of the second contact hole.

Abstract: A method for forming a self-aligned contact is provided. In an embodiment, a metal gate is formed on a substrate, and a gate spacer is formed adjacent the metal gate. A conductive plug is formed over the substrate, with the gate spacer disposed between the metal gate and the conductive plug. The metal gate and the conductive plug are recessed. A first dielectric layer is deposited over the gate spacer, over the metal gate, over the conductive plug, and along sidewalls of the metal gate. A first opening is formed in the first dielectric layer exposing the metal gate, and a second opening is formed in the first dielectric layer exposing the conductive plug. The first opening and the second opening are filled with a first conductive material.

Abstract: A method for manufacturing a semiconductor device is provided, including forming a plurality of fins on a semiconductor substrate, and forming source/drain regions on the fins. The source/drain regions have an uneven surface with a mean surface roughness, Ra, of about 10 nm to about 50 nm. A smoothing layer is formed on the source/drain regions filling the uneven surface. An etch stop layer is formed overlying the smoothing layer. A portion of the etch stop layer is removed to expose a portion of the smoothing layer. The exposed smoothing layer is removed, and a contact layer is formed on the source/drain regions.

Abstract: A method includes forming a first and a second contact opening to reveal a first and a second source/drain region, respectively, forming a mask layer having a first and a second portion in the first and the second contact openings, respectively, forming a first and a second sacrificial ILD in the first and the second contact openings, respectively, removing the first sacrificial ILD from the first contact opening, filling a filler in the first contact opening, and etching the second sacrificial ILD. The filler protects the first portion of the mask layer from being etched. An ILD is formed in the second contact opening and on the second portion of the mask layer. The filler and the first portion of the mask layer are removed using a wet etch to reveal the first contact opening. A contact plug is formed in the first contact opening.

Abstract: In a method of manufacturing a semiconductor device, an interlayer dielectric (ILD) layer is formed over an underlying structure. The underlying structure includes gate structures, each having a metal gate and a cap insulating layer disposed over the metal gate, source/drain epitaxial layers disposed between two adjacent gate structures, and an etching-stop layer (ESL) covering the source/drain epitaxial layers. An opening is formed in the ILD layer by etching. A dielectric filling layer is formed in the opening. By using wet etching, the ILD layer disposed above the source/drain epitaxial layers is removed. The ESL disposed on the source/drain epitaxial layers is removed, thereby at least partially exposing the source/drain epitaxial layers. A conductive material is formed over the exposed source/drain epitaxial layers.

Abstract: A method includes forming a transistor including forming a source/drain region on a side of a dummy gate stack, forming a first Inter-Layer Dielectric (ILD) covering the source/drain region, and replacing the dummy gate stack with a replacement gate stack. The method further includes forming a second ILD over the first ILD and the replacement gate stack, and forming a lower source/drain contact plug electrically coupling to the source/drain region. The lower source/drain contact plug penetrates through both the first ILD and the second ILD. A third ILD is formed over the second ILD. A gate contact plug is formed in the second ILD and the third ILD. An upper source/drain contact plug is formed overlapping and contacting the lower source/drain contact plug. The upper source/drain contact plug penetrates through the third ILD. The upper source/drain contact plug and the gate contact plug are formed of different materials.

Abstract: A method includes forming a first and a second contact opening to reveal a first and a second source/drain region, respectively, forming a mask layer having a first and a second portion in the first and the second contact openings, respectively, forming a first and a second sacrificial ILD in the first and the second contact openings, respectively, removing the first sacrificial ILD from the first contact opening, filling a filler in the first contact opening, and etching the second sacrificial ILD. The filler protects the first portion of the mask layer from being etched. An ILD is formed in the second contact opening and on the second portion of the mask layer. The filler and the first portion of the mask layer are removed using a wet etch to reveal the first contact opening. A contact plug is formed in the first contact opening.

Abstract: A semiconductor device includes a gate structure disposed over a substrate, and sidewall spacers disposed on both side walls of the gate structure. The sidewall spacers includes at least four spacer layers including first to fourth spacer layers stacked in this order from the gate structure.

Abstract: In a method of manufacturing a semiconductor device, an interlayer dielectric (ILD) layer is formed over an underlying structure. The underlying structure includes gate structures, each having a metal gate and a cap insulating layer disposed over the metal gate, source/drain epitaxial layers disposed between two adjacent gate structures, and an etching-stop layer (ESL) covering the source/drain epitaxial layers. An opening is formed in the ILD layer by etching. A dielectric filling layer is formed in the opening. By using wet etching, the ILD layer disposed above the source/drain epitaxial layers is removed. The ESL disposed on the source/drain epitaxial layers is removed, thereby at least partially exposing the source/drain epitaxial layers. A conductive material is formed over the exposed source/drain epitaxial layers.

Abstract: In a method of manufacturing a semiconductor device, an interlayer dielectric (ILD) layer is formed over an underlying structure. The underlying structure includes gate structures, each having a metal gate and a cap insulating layer disposed over the metal gate, source/drain epitaxial layers disposed between two adjacent gate structures, and an etching-stop layer (ESL) covering the source/drain epitaxial layers. An opening is formed in the ILD layer by etching. A dielectric filling layer is formed in the opening. By using wet etching, the ILD layer disposed above the source/drain epitaxial layers is removed. The ESL disposed on the source/drain epitaxial layers is removed, thereby at least partially exposing the source/drain epitaxial layers. A conductive material is formed over the exposed source/drain epitaxial layers.

Abstract: A method for manufacturing a semiconductor device is provided, including forming a plurality of fins on a semiconductor substrate, and forming source/drain regions on the fins. The source/drain regions have an uneven surface with a mean surface roughness, Ra, of about 10 nm to about 50 nm. A smoothing layer is formed on the source/drain regions filling the uneven surface. An etch stop layer is formed overlying the smoothing layer. A portion of the etch stop layer is removed to expose a portion of the smoothing layer. The exposed smoothing layer is removed, and a contact layer is formed on the source/drain regions.

Abstract: Self-aligned contacts are provided. In an embodiment the self-aligned contacts are formed by partially removing a first dielectric material from adjacent to a gate electrode and fully removing a second dielectric material from adjacent to the gate electrode. A conductive material is deposited into the regions of the removed first dielectric material and the second dielectric material, and the conductive material and metal gates are recessed below a spacer. A dielectric layer is deposited over the recessed conductive material and the recessed metal gates, and the self-aligned contacts are formed through the dielectric layer.

Abstract: A semiconductor device includes a gate structure disposed over a substrate, and sidewall spacers disposed on both side walls of the gate structure. The sidewall spacers includes at least four spacer layers including first to fourth spacer layers stacked in this order from the gate structure.

Abstract: A method for manufacturing a semiconductor device is provided, including forming a plurality of fins on a semiconductor substrate, and forming source/drain regions on the fins. The source/drain regions have an uneven surface with a mean surface roughness, Ra, of about 10 nm to about 50 nm. A smoothing layer is formed on the source/drain regions filling the uneven surface. An etch stop layer is formed overlying the smoothing layer. A portion of the etch stop layer is removed to expose a portion of the smoothing layer. The exposed smoothing layer is removed, and a contact layer is formed on the source/drain regions.