Patents by Inventor Fu-Kai Yang

Fu-Kai Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220165860
    Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a first plurality of channel members over a backside dielectric layer, a second plurality of channel members over the backside dielectric layer, a silicide feature disposed in the backside dielectric layer, and a source/drain feature disposed over the silicide feature and extending between the first plurality of channel members and the second plurality of channel members. The silicide feature extends through an entire depth of the backside dielectric layer.
    Type: Application
    Filed: November 24, 2020
    Publication date: May 26, 2022
    Inventors: Chen-Hung Tsai, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 11342444
    Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Gang Chen, Tai-Chun Huang, Ming-Chang Wen, Shu-Yuan Ku, Fu-Kai Yang, Tze-Liang Lee, Yung-Cheng Lu, Yi-Ting Fu
  • Publication number: 20220153404
    Abstract: The present application provides an unmanned aerial vehicle (UAV) for a long duration flight. An exemplary UAV may include a UAV body assembly. The UAV may also include a flight control system (FCS) coupled to the UAV body assembly. The UAV may further include a motor coupled to the UAV body assembly at one end and coupled to a propeller at the other end. The FCS is communicatively connected to the motor. A center of gravity (CG) of the UAV is at a point between 21% and 25% of a mean aerodynamic chord (MAC) of the UAV.
    Type: Application
    Filed: February 1, 2022
    Publication date: May 19, 2022
    Applicant: GEOSAT Aerospace & Technology
    Inventors: Fu-Kai YANG, Chien-Hsun LIAO, Yi-Feng CHENG, Di-Yang WANG, Meng-Yan SHEN
  • Publication number: 20220130961
    Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.
    Type: Application
    Filed: January 10, 2022
    Publication date: April 28, 2022
    Inventors: I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chun-An Lin, Wei-Yuan Lu, Guan-Ren Wang, Peng Wang
  • Patent number: 11302802
    Abstract: The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device according to one embodiment of the present disclosure includes a first fin-shaped structure extending lengthwise along a first direction over a substrate, a first epitaxial feature over a source/drain region of the first fin-shaped structure, a gate structure disposed over a channel region of the first fin-shaped structure and extending along a second direction perpendicular to the first direction, and a source/drain contact over the first epitaxial feature. The bottommost surface of the gate structure is closer to the substrate than a bottommost surface of the source/drain contact.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Heng Wang, Chun-Han Chen, I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 11289383
    Abstract: An embodiment method includes: forming fins extending from a semiconductor substrate; depositing an inter-layer dielectric (ILD) layer on the fins; forming masking layers on the ILD layer; forming a cut mask on the masking layers, the cut mask including a first dielectric material, the cut mask having first openings exposing the masking layers, each of the first openings surrounded on all sides by the first dielectric material; forming a line mask on the cut mask and in the first openings, the line mask having slot openings, the slot openings exposing portions of the cut mask and portions of the masking layers, the slot openings being strips extending perpendicular to the fins; patterning the masking layers by etching the portions of the masking layers exposed by the first openings and the slot openings; and etching contact openings in the ILD layer using the patterned masking layers as an etching mask.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Yuan Chen, Jui-Ping Lin, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 11276643
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a power rail; a bottom semiconductor layer formed over the dielectric layer; a backside spacer formed along a sidewall of the bottom semiconductor layer; a conductive feature contacting a sidewall of the dielectric layer and a sidewall of the backside spacer; channel semiconductor layers over the bottom semiconductor layer, wherein the channel semiconductor layers are stacked up and separated from each other; a metal gate structure wrapping each of the channel semiconductor layers; and an epitaxial source/drain (S/D) feature contacting a sidewall of each of the channel semiconductor layers, wherein the epitaxial S/D feature contacts the conductive feature, and the conductive feature contacts the power rail.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: March 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Yu Huang, Jason Yao, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 11267555
    Abstract: The present application provides an unmanned aerial vehicle (UAV) for a long duration flight. An exemplary UAV may include a UAV body assembly. The UAV may also include a flight control system (FCS) coupled to the UAV body assembly. The UAV may further include a motor coupled to the UAV body assembly at one end and coupled to a propeller at the other end. The FCS is communicatively connected to the motor. A center of gravity (CG) of the UAV is at a point between 21% and 25% of a mean aerodynamic chord (MAC) of the UAV.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: March 8, 2022
    Assignee: GEOSAT AEROSPACE & TECHNOLOGY
    Inventors: Fu-Kai Yang, Chien-Hsun Liao, Yi-Feng Cheng, Di-Yang Wang, Meng-Yan Shen
  • Patent number: 11264393
    Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Lin Chen, Chao-Yuan Chang, Ping-Wei Wang, Fu-Kai Yang, Ting Fang, I-Wen Wu, Shih-Hao Lin
  • Patent number: 11264383
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a first gate structure formed over a fin structure, and a conductive layer formed over the first gate structure. The FinFET device structure includes a first capping layer formed over the conductive layer, and a top surface of the conductive layer is in direct contact with a bottom surface of the first capping layer.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Han Chen, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Jr-Hung Li, Bo-Cyuan Lu
  • Patent number: 11244832
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a metal gate structure formed over the substrate. The semiconductor structure further includes a sealing layer comprising an inner sidewall and an outermost sidewall. In addition, the inner sidewall is in direct contact with the metal gate structure and the outermost sidewall is away from the metal gate structure. The semiconductor structure further includes a mask structure formed over the metal gate structure. In addition, the mask structure has a straight sidewall over the metal gate structure and a sloped sidewall extending from the inner sidewall of the sealing layer and passing over the outmost sidewall of the sealing layer.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: February 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Ying Lin, Mei-Yun Wang, Hsien-Cheng Wang, Fu-Kai Yang, Shih-Wen Liu, Hsiao-Chiu Hsu
  • Patent number: 11239309
    Abstract: Semiconductor devices and methods of fabricating semiconductor devices are provided. The present disclosure provides a semiconductor device that includes a first fin structure and a second fin structure each extending from a substrate; a first gate segment over the first fin structure and a second gate segment over the second fin structure; a first isolation feature separating the first and second gate segments; a first source/drain (S/D) feature over the first fin structure and adjacent to the first gate segment; a second S/D feature over the second fin structure and adjacent to the second gate segment; and a second isolation feature also disposed in the trench. The first and second S/D features are separated by the second isolation feature, and a composition of the second isolation feature is different from a composition of the first isolation feature.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: February 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Wen Wu, Fu-Kai Yang, Chen-Ming B. Lee, Mei-Yun Wang, Jr-Hung Li, Bo-Cyuan Lu
  • Publication number: 20220028983
    Abstract: A method according to the present disclosure includes receiving a workpiece that includes a gate structure, a first gate spacer feature, a second gate spacer feature, a gate-top dielectric feature over the gate structure, the first gate spacer feature and the second gate spacer feature, a first source/drain feature over a first source/drain region, a second source/drain feature over a second source/drain region, a first dielectric layer over the first source/drain feature, and a second dielectric layer over the second source/drain feature. The method further includes replacing a top portion of the first dielectric layer with a first hard mask layer, forming a second hard mask layer over the first hard mask layer while the second dielectric layer is exposed, etching the second dielectric layer to form a source/drain contact opening and to expose the second source/drain feature, and forming a source/drain contact over the second source/drain feature.
    Type: Application
    Filed: July 22, 2020
    Publication date: January 27, 2022
    Inventors: Ting Fang, Chung-Hao Cai, Ruei-Ping Lin, Jason Yao, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20220028786
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a power rail; a bottom semiconductor layer formed over the dielectric layer; a backside spacer formed along a sidewall of the bottom semiconductor layer; a conductive feature contacting a sidewall of the dielectric layer and a sidewall of the backside spacer; channel semiconductor layers over the bottom semiconductor layer, wherein the channel semiconductor layers are stacked up and separated from each other; a metal gate structure wrapping each of the channel semiconductor layers; and an epitaxial source/drain (S/D) feature contacting a sidewall of each of the channel semiconductor layers, wherein the epitaxial S/D feature contacts the conductive feature, and the conductive feature contacts the power rail.
    Type: Application
    Filed: July 22, 2020
    Publication date: January 27, 2022
    Inventors: Po-Yu Huang, Jason Yao, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 11222951
    Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: January 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chun-An Lin, Wei-Yuan Lu, Guan-Ren Wang, Peng Wang
  • Patent number: 11217492
    Abstract: A method includes providing a structure that includes a substrate, a first gate structure and a second gate structure over the substrate, and a first source/drain (S/D) feature and a second S/D feature over the substrate. The first S/D feature is adjacent to the first gate structure, the second S/D feature is adjacent to the second gate structure, the first S/D feature is configured for an n-type transistor, and the second S/D feature is configured for a p-type transistor. The method further includes introducing a p-type dopant into both the first and the second S/D features. After the introducing of the p-type dopant, the method further includes performing an etching process to the first and the second S/D features, wherein the etching process etches the first S/D feature faster than it etches the second S/D feature.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: January 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Ming Koh, Chen-Ming Lee, I-Wen Wu, Fu-Kai Yang, Jia-Heng Wang, Mei-Yun Wang
  • Publication number: 20210375695
    Abstract: An embodiment method includes: forming fins extending from a semiconductor substrate; depositing an inter-layer dielectric (ILD) layer on the fins; forming masking layers on the ILD layer; forming a cut mask on the masking layers, the cut mask including a first dielectric material, the cut mask having first openings exposing the masking layers, each of the first openings surrounded on all sides by the first dielectric material; forming a line mask on the cut mask and in the first openings, the line mask having slot openings, the slot openings exposing portions of the cut mask and portions of the masking layers, the slot openings being strips extending perpendicular to the fins; patterning the masking layers by etching the portions of the masking layers exposed by the first openings and the slot openings; and etching contact openings in the ILD layer using the patterned masking layers as an etching mask.
    Type: Application
    Filed: May 27, 2020
    Publication date: December 2, 2021
    Inventors: Chien-Yuan Chen, Ruei-Ping Lin, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20210366786
    Abstract: In an embodiment, a device includes: a semiconductor substrate; a first fin extending from the semiconductor substrate; a second fin extending from the semiconductor substrate; an epitaxial source/drain region including: a main layer in the first fin and the second fin, the main layer including a first semiconductor material, the main layer having a upper faceted surface and a lower faceted surface, the upper faceted surface and the lower faceted surface each being raised from respective surfaces of the first fin and the second fin; and a semiconductor contact etch stop layer (CESL) contacting the upper faceted surface and the lower faceted surface of the main layer, the semiconductor CESL including a second semiconductor material, the second semiconductor material being different from the first semiconductor material.
    Type: Application
    Filed: May 22, 2020
    Publication date: November 25, 2021
    Inventors: Chun-Han Chen, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20210367054
    Abstract: A device includes a gate stack; a gate spacer on a sidewall of the gate stack; a source/drain region adjacent the gate stack; a silicide; and a source/drain contact electrically connected to the source/drain region through the silicide. The silicide includes a conformal first portion in the source/drain region, the conformal first portion comprising a metal and silicon; and a conformal second portion over the conformal first portion, the conformal second portion further disposed on a sidewall of the gate spacer, the conformal second portion comprising the metal, silicon, and nitrogen.
    Type: Application
    Filed: May 22, 2020
    Publication date: November 25, 2021
    Inventors: Kai-Di Tzeng, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 11152486
    Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes a first gate stack, a second gate stack, a first source/drain feature disposed between the first and second gate stacks, and a source/drain contact over and electrically coupled to the first source/drain feature. The source/drain contact is spaced apart from each of the first and second gate stacks by an inner spacer disposed on sidewalls of the source/drain contact, a first air gap, a first gate spacer, and a second air gap separated from the first air gap by the first gate spacer.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: October 19, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yu Yang, Kai-Hsuan Lee, Wei-Yang Lee, Fu-Kai Yang, Yen-Ming Chen