Patents by Inventor Fu Peng

Fu Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250141021
    Abstract: A battery pack includes a battery seat and a lock assembly. The lock assembly has a button disposed in the battery seat and has two opposite first inclined surfaces, and two lock members disposed in the battery seat and located at two opposite sides of the button. The lock members each have a second inclined surface abutted against the first inclined surface of the button, such that the lock members are pushed closer to each other by the button to move from a lock position to an unlock position, thus unlocking the battery pack from an electronic device. Thus, the present invention allows a user to hold the battery seat by one hand and operate the button by an index finger of the same hand for achieving an unlocking effect. Further, the present invention provides a method of disassembling the battery pack from the electronic device.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 1, 2025
    Inventors: Yu-Chia HUANG, Fu-Peng CHOU
  • Publication number: 20240373784
    Abstract: A lift detection mechanism of a mowing robot includes a wheel set, a movable member, a transmitter, and a receiver. The wheel set has an axle rotatably and movably penetrated into a fixed seat, a wheel connected to the axle and located outside of the fixed seat, and a fixing member disposed to the axle and located in the fixed seat. The movable member is disposed to the axle and located in the fixed seat. One of the transmitter and the receiver is disposed to the movable member, and the other of the transmitter and the receiver is disposed to the fixed seat. As such, when the mowing robot is lifted by a user, the movable member is driven by an elastic member to move downwards until the transmitter and the receiver are staggered. As such, blades are controlled to stop working for preventing the user from being cut.
    Type: Application
    Filed: May 3, 2024
    Publication date: November 14, 2024
    Inventors: Yu-Chia HUANG, Fu-Peng CHOU
  • Publication number: 20240375286
    Abstract: A visual identification positioning system includes a first positioning member, a second positioning member, and a mowing robot. The mowing robot has a visual identification unit and a computation unit. The visual identification unit identifies a first identification feature of the first positioning member and a second identification feature of the second positioning member to generate first and second signals to the computation unit. The computation unit computes a first coordinate, a second coordinate, a first distance between the mowing robot and the first coordinate, and a second distance between the mowing robot and the second coordinate according to the first and second signals, and defines first and second ranges with the first and second coordinates as centers according to the first and second distances, and computes a coordinate of an intersection of the first and second ranges as a current location coordinate of the mowing robot.
    Type: Application
    Filed: March 28, 2024
    Publication date: November 14, 2024
    Inventors: Yu-Chia HUANG, Fu-Peng CHOU
  • Publication number: 20240373781
    Abstract: A mowing system includes a charging station, a base station, and a mowing robot. The base station and the charging station are set independently from each other. The base station has a first communication unit and a first GPS antenna. The mowing robot has a second GPS antenna and a control unit electrically connected with the second GPS antenna and wirelessly connected with the first GPS antenna, such that the control unit receives a first GPS signal obtained by the first GPS antenna and a second GPS signal obtained by the second GPS antenna and determines a positioning coordinate of the mower robot according to the first GPS signal and the second GPS signal. As such, the installation position of the base station is not restricted by the surrounding environment or the charging station so as to enhance positioning precision.
    Type: Application
    Filed: May 3, 2024
    Publication date: November 14, 2024
    Inventors: Yu-Chia HUANG, Fu-Peng CHOU
  • Publication number: 20240380358
    Abstract: A GPS positioning stake includes a supporting pole, a base connected with the supporting pole and having a GPS positioning module and a rotation axle, an adjustment board having an axle sleeving portion pivotably connected with the rotation axle and a solar panel providing electric energy for the operation of the GPS positioning module, and an angle adjusting device including a first gear fixedly sleeved onto the rotation axle, a second gear sleeved onto the rotation axle and located in the axle sleeving portion, an elastic member, and an operation member. The first and second gears engage when the operation member locks, disabling the adjustment board from rotation relative to the rotation axle, and separate when the operation member unlocks, enabling the adjustment board to drive the second gear to rotate relative to the rotation axle for adjusting the solar panel's light receiving angle for better energy conversion efficiency.
    Type: Application
    Filed: May 3, 2024
    Publication date: November 14, 2024
    Inventors: Yu-Chia HUANG, Fu-Peng CHOU
  • Patent number: 11664442
    Abstract: A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chang Huang, Fu-Peng Lu, Chun-Chang Liu, Chen-Chiu Huang
  • Patent number: 11608205
    Abstract: A head of a tag device having a body, at least one row of negative-pressure through holes and at least one row of positive-pressure through holes. The body has a first surface and a second surface. The rows of negative and positive-pressure through holes are formed through the first and second surfaces of the body and arranged along a long-axis direction. Two negative and positive-pressure through holes at both ends of the corresponding row of negative and positive-pressure through holes are respectively close to the short sides of the body. Therefore, an effective labeling area is distributed between two short sides. The head of the tag device of the present invention provides a stable labeling operation for different products where different components are mounted and increases units per hour (UPH).
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: March 21, 2023
    Assignee: Powertech Technology Inc.
    Inventors: Ching-Chia Yang, Shin-Kung Chen, Yuan-Jung Lu, Yen-Yu Chen, Hsing-Fu Peng, Pao-Chen Lin
  • Publication number: 20220097891
    Abstract: A manual labeling device is disclosed. The manual labeling device has a platform, a plurality of positioning elements and a pivoting device. The platform has a labeling area. The positioning elements are mounted on the platform and around the labeling area. The pivoting device is pivotally mounted on one side of the platform and has a pivot shaft and a pivot arm. The operator manually places one product in the labeling area of the platform and the product is fixed in the labeling area by the positioning elements. The operator only pivots the pivot arm and the pivot arm directly aligns with the labeling area. Therefore, it does not take times to align the tool and the labeling area before attaching the label and the label attaching task is simplified to increase the productivity and quality of labeling (units per hour; UPH).
    Type: Application
    Filed: March 30, 2021
    Publication date: March 31, 2022
    Applicant: Powertech Technology Inc.
    Inventors: Yen Yu CHEN, Shin-Kung CHEN, Yuan-Jung LU, Hsing-Fu PENG
  • Publication number: 20220002020
    Abstract: A head of a tag device having a body, at least one row of negative-pressure through holes and at least one row of positive-pressure through holes. The body has a first surface and a second surface. The rows of negative and positive-pressure through holes are formed through the first and second surfaces of the body and arranged along a long-axis direction. Two negative and positive-pressure through holes at both ends of the corresponding row of negative and positive-pressure through holes are respectively close to the short sides of the body. Therefore, an effective labeling area is distributed between two short sides. The head of the tag device of the present invention provides a stable labeling operation for different products where different components are mounted and increases units per hour (UPH).
    Type: Application
    Filed: October 15, 2020
    Publication date: January 6, 2022
    Applicant: Powertech Technology Inc.
    Inventors: Ching-Chia YANG, Shin-Kung CHEN, Yuan-Jung LU, Yen-Yu CHEN, Hsing-Fu PENG, Pao-Chen LIN
  • Publication number: 20210050431
    Abstract: A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.
    Type: Application
    Filed: October 19, 2020
    Publication date: February 18, 2021
    Inventors: Kuo-Chang Huang, Fu-Peng Lu, Chun-Chang Liu, Chen-Chiu Huang
  • Patent number: 10811519
    Abstract: A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: October 20, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chang Huang, Fu-Peng Lu, Chun-Chang Liu, Chen-Chiu Huang
  • Publication number: 20190288087
    Abstract: A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.
    Type: Application
    Filed: June 3, 2019
    Publication date: September 19, 2019
    Inventors: Kuo-Chang Huang, Fu-Peng Lu, Chun-Chang Liu, Chen-Chiu Huang
  • Patent number: 10312348
    Abstract: A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chang Huang, Fu-Peng Lu, Chun-Chang Liu, Chen-Chiu Huang
  • Patent number: 10304931
    Abstract: The present invention belongs to the field of semiconductor technology and relates to a polarization-doped enhancement mode HEMT device. The technical solution of the present invention grows the first barrier layer and the second barrier layer that contain gradient Al composition sequentially on the buffer layer. The gradient trends of the two layers are opposite. The three-dimensional electron gas (3DEG) and the three-dimensional hole gas (3DHG) are induced and generated in the barrier layers due to the inner polarization difference respectively. A trench insulated gate structure is at one side of the source which is away from the metal drain and is in contact with the source. First, since the highly concentrated electrons exist in the entire first barrier layer, the on-state current is improved greatly. Second, the vertical conductive channel between the source and the 3DEG are pinched off by the 3DHG, so as to realize the enhancement mode.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: May 28, 2019
    Assignee: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA
    Inventors: Xiaorong Luo, Fu Peng, Chao Yang, Jie Wei, Siyu Deng, Dongfa Ouyang, Bo Zhang
  • Publication number: 20190157419
    Abstract: A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.
    Type: Application
    Filed: February 7, 2018
    Publication date: May 23, 2019
    Inventors: Kuo-Chang Huang, Fu-Peng Lu, Chun-Chang Liu, Chen-Chiu Huang
  • Publication number: 20180294335
    Abstract: The present invention belongs to the field of semiconductor technology and relates to a polarization-doped enhancement mode HEMT device. The technical solution of the present invention grows the first barrier layer and the second barrier layer that contain gradient Al composition sequentially on the buffer layer. The gradient trends of the two layers are opposite. The three-dimensional electron gas (3DEG) and the three-dimensional hole gas (3DHG) are induced and generated in the barrier layers due to the inner polarization difference respectively. A trench insulated gate structure is at one side of the source which is away from the metal drain and is in contact with the source. First, since the highly concentrated electrons exist in the entire first barrier layer, the on-state current is improved greatly. Second, the vertical conductive channel between the source and the 3DEG are pinched off by the 3DHG, so as to realize the enhancement mode.
    Type: Application
    Filed: June 14, 2017
    Publication date: October 11, 2018
    Applicant: University of Electronic Science and Technology of China
    Inventors: Xiaorong LUO, Fu PENG, Chao YANG, Jie WEI, Siyu DENG, Dongfa OUYANG, Bo ZHANG
  • Publication number: 20180076402
    Abstract: A method of forming a transistor includes: forming a stack structure including a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer on a substrate; patterning the first insulating layer, the second conductive layer, and the second insulating layer to form at least one opening passing through the first insulating layer, the second conductive layer, and the second insulating layer; forming a semiconductor layer over the second insulating layer and filling the opening; removing the portion of the semiconductor layer over the second insulating layer, in which the portion of the semiconductor layer filled in the opening constitutes at least one semiconductor channel; and forming a third conductive layer over the semiconductor channel.
    Type: Application
    Filed: April 5, 2017
    Publication date: March 15, 2018
    Inventors: Hsiao-Wen ZAN, Shao-Fu PENG, Cheng-Hang HSU
  • Patent number: 9917268
    Abstract: A method of forming a transistor includes: forming a stack structure including a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer on a substrate; patterning the first insulating layer, the second conductive layer, and the second insulating layer to form at least one opening passing through the first insulating layer, the second conductive layer, and the second insulating layer; forming a semiconductor layer over the second insulating layer and filling the opening; removing the portion of the semiconductor layer over the second insulating layer, in which the portion of the semiconductor layer filled in the opening constitutes at least one semiconductor channel; and forming a third conductive layer over the semiconductor channel.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: March 13, 2018
    Assignee: E Ink Holdings Inc.
    Inventors: Hsiao-Wen Zan, Shao-Fu Peng, Cheng-Hang Hsu
  • Patent number: 9431527
    Abstract: An enhancement mode HEMT, including: a substrate layer; a buffer layer; barrier layers; drain electrodes; reverse polarization semiconductor layers; source electrodes; an insulated gate dielectric; and a metal gate electrode The buffer layer is disposed on the substrate layer, and the barrier layers are disposed on the buffer layer. Interfaces between the buffer layer and the barrier layers are provided with first heterojunctions having a two-dimensional electron gas (2DEG) channel. The drain electrodes are disposed at one end of the upper surfaces of the barrier layers and form Ohmic contact with the barrier layers. The reverse polarization semiconductor layers are disposed on the upper surfaces of the barrier layers and are able to produce inversed polarization with the barrier layers. The interfaces between reverse polarization semiconductor layers and barrier layers are provided with second heterojunctions having two-dimensional hole gas (2DHG).
    Type: Grant
    Filed: December 27, 2015
    Date of Patent: August 30, 2016
    Assignee: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA
    Inventors: Xiaorong Luo, Jiayun Xiong, Chao Yang, Jie Wei, Junfeng Wu, Fu Peng, Bo Zhang
  • Patent number: 8915516
    Abstract: A convertible tandem stroller frame is capable of locking in a tandem stroller mode for installing a second seat thereby concurrently transporting two occupants, and capable of converting said mode into a single seat mode for transporting single occupant by simply manipulating a release actuator at a front portion of the convertible tandem stroller frame. The convertible tandem stroller frame may include a front rack, a rear rack, at least a longitudinal telescopic mechanism and at least a locking mechanism. The front rack and the rear rack are lockably and adjustably connected by the longitudinal telescopic mechanism, so as to be extended into the tandem stroller mode and be retracted into the single seat mode. The locking mechanism is associated with the release actuator for locking and un-locking the longitudinal telescopic mechanism by manipulating in front of the convertible tandem stroller frame.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: December 23, 2014
    Assignee: Lerado (Zhong Shan) Industrial Co., Ltd.
    Inventors: Cheng-Fan Yang, Chen-Tai Chang, Sheng-Po Hung, Fu-Peng Chou