TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
A method of forming a transistor includes: forming a stack structure including a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer on a substrate; patterning the first insulating layer, the second conductive layer, and the second insulating layer to form at least one opening passing through the first insulating layer, the second conductive layer, and the second insulating layer; forming a semiconductor layer over the second insulating layer and filling the opening; removing the portion of the semiconductor layer over the second insulating layer, in which the portion of the semiconductor layer filled in the opening constitutes at least one semiconductor channel; and forming a third conductive layer over the semiconductor channel.
This application claims priority to China Application Serial Number 201610817754.5, filed Sep. 13, 2016, the entity of which is incorporated herein by reference.
BACKGROUND Technical FieldThe present disclosure relates to a transistor and a method of manufacturing the transistor.
Description of Related ArtTransistor is a kind of solid semiconductor devices which can be used to amplify, switch, regulate, and/or modulate signals and with other functions. The carrier mobility of the semiconductor in the transistor is an important factor which affects the performance of the transistor. Hence, contemporary researchers in studying semiconductor are dedicated to achieving higher carrier mobility.
SUMMARYOne aspect of the present disclosure is to provide a transistor having a high carrier mobility. The transistor includes a first electrode, a first insulating layer, a second electrode, a second insulating layer, a semiconductor channel layer and a third electrode. The first insulating layer is positioned over the first electrode. The second electrode is positioned over the first insulating layer. The second insulating layer is positioned over the second electrode. The semiconductor channel layer is extended upwards from the first electrode and passes through the first insulating layer, the second electrode, and the second insulating layer. The third electrode is positioned over the second insulating layer and in contact with a top surface of the semiconductor channel layer.
According to some embodiments of the present disclosure, the semiconductor channel layer has a sidewall in contact with the first insulating layer, the second electrode, and the second insulating layer, in which the semiconductor channel layer has a crystal plane with Miller Index (010).
According to some embodiments of the present disclosure, the third electrode includes a hole injection layer and a metal layer on the hole injection layer, in which the hole injection layer is in contact with the top surface of the semiconductor channel layer.
According to some embodiments of the present disclosure, the second insulating layer includes an insulating polymer laser and a hard mask layer. The insulating polymer layer is in contact with the second electrode, and the hard mask layer is positioned on the insulating polymer layer.
According to some embodiments of the present disclosure, the semiconductor channel layer has a height substantially equal to the summed thickness of the first insulating layer, the second electrode, and the second insulating layer.
Another aspect of the present disclosure is to provide a method of manufacturing a transistor with excellent performance. The method includes the following operation: sequentially forming a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer in stack on a substrate; patterning the first insulating layer, the second conductive layer and the second insulating layer to form at least one opening passing through the first insulating layer, the second conductive layer, and the second insulating layer; forming a semiconductor layer over the second insulating layer and filling the opening; removing a portion of the semiconductor layer positioned over the second insulating layer, in which a remained portion of the semiconductor layer in the opening form a semiconductor channel; and forming a third conductive layer over the semiconductor channel.
According to some embodiments of the present disclosure, forming the third conductive layer over the semiconductor channel includes: forming a hole injection layer on the semiconductor channel; and forming a metal layer on the hole injection layer.
According to some embodiments of the present disclosure, patterning the first insulating layer, the second conductive layer, and the second insulating layer includes the following steps: disposing a plurality of particles on the second insulating layer; depositing a mask layer covering the particles and the second insulating layer; removing the particles and a portion of the mask layer positioned on the particles to form a patterned mask layer on the second insulating layer, wherein the patterned mask layer has a plurality of apertures exposing a portion of the second insulating layer; and sequentially etching the second insulating layer, the second conductive layer, and the first insulating layer through the apertures of the patterned mask layer to form the opening passing through the first insulating layer, the second conductive layer, and the second insulating layer.
According to some embodiments of the present disclosure, sequentially etching the second insulating layer, the second conductive layer, and the first insulating layer includes: applying a dry etching process to etch the second insulating layer; applying a wet etching process to etch the second conductive layer; and applying a dry etching process to etch the first insulating layer.
According to some embodiments of the present disclosure, the semiconductor layer includes a polymeric semiconductor, and a portion of the semiconductor layer filled in the opening has a crystal plane with Miller Index (010), whereas a portion of the semiconductor layer positioned over the second insulating layer has a crystal plane with Miller Index (100).
It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the present disclosure as claimed.
The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and together with the description, serve to explain the principles of the present disclosure.
In the drawings,
Reference will now be made in detail to the present embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. The example is not the only way to implement or utilize the present disclosure. The embodiments disclosed below may be combined or replaced each other in some better way. These combinations may not be described or explained further. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In order to simplify the drawing, some well-known structure and device may be illustrated in the Figures schematically.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
In operation 11, a stack structure which includes a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer is formed on a substrate.
Referring to
Referring to
Referring to
Referring to
In operation 15, a third conductive layer is formed over the semiconductor channels. Referring to
Therefore, another aspect of the present disclosure is to provide a transistor.
The first electrode 210 is disposed on the substrate 100, and the first electrode 210, for example, may be made of metal, or transparent conductive material such as indium tin oxide. In some embodiments, the first electrode 210 is the collector of the transistor 200. In yet some embodiments, the first electrode 210 is the emitter of the transistor 200. The thickness of the first electrode 210 may be varied, according to the requirement, for example ranging from approximately tens of nanometers to tens of micrometers.
The first insulating layer 220 is over the first electrode 210. The first insulating layer 220 may be, for example, made of organic insulating material or inorganic insulating material. Illustrative examples of the organic insulating material include polyvinylpyrrolidone(PVP), polyamide, or the like. Illustrative examples of inorganic insulating material include silicon oxide, silicon nitride, and the like. The thickness of the first insulating layer 220 is not particularly limited. In examples, the thickness of the first insulating layer 220 may be ranged from approximately tens of nanometers to tens of micrometers.
The second electrode 230 is positioned over the first insulating layer 220. The second electrode 230 may include metal material such as aluminum, neodymium, nickel, copper and/or silver, for example. The thickness of the second electrode 230 may be varied, according to the requirement, for example ranging from approximately tens of nanometers to tens of micrometers.
The second insulating layer 240 is positioned over the second electrode 230. In some embodiments, the first insulating layer 220, the second electrode 230 and the second insulating layer 240 have substantially the same pattern in a plan view. In some embodiments, one or more openings which pass through the first insulating layer 220, the second electrode 230 and the second insulating layer 240 are formed by using an identical patterned mask layer to pattern the first insulating layer 220, the second electrode 230 and the second insulating layer 240. The second insulating layer 240 may be a single-layered or multiple-layered structure. In one embodiment, as depicted in
One or more semiconductor channel layers 250 extend upwards from the first electrode 210 and pass through the first insulating layer 220, the second electrode 230 and the second insulating layer 240. In various embodiments, the side wall 250s of the each semiconductor channel layer 250 touches the first insulating layer 220, the second electrode 230 and the second insulating layer 240. In some embodiments, the semiconductor channel layer 250 is made of organic semiconductor material such as poly(3-hexylthiophene-2,5-diyl) or other organic semiconductor material. In some examples, the semiconductor channel layer 250 is face-on arrangement orientation. In some examples, the semiconductor channel layer 250 has crystal planes with Miller Index (010).
A third electrode 260 is positioned over the second insulating layer 240, and touches the top surface of the semiconductor channel layer 250. In some embodiments, the third electrode 260 includes hole injection layer 162 and a metal layer 164 on the hole injection layer 162. The hole injection layer 162 touches the top surface of the semiconductor channel layer 250. In some embodiments, the hole injection layer 262 may be made of molybdenum trioxide(MoO3) or other suitable hole injection materials. The metal layer 164 may include metallic materials such as fore example aluminum, neodymium, nickel, copper and/or silver.
In some embodiments, the height d1 of the semiconductor channel layer 250 substantially equals a summed thickness T of the first insulating layer 220, the second electrode 230 and the second insulating layer 240.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of the present disclosure provided they fall within the scope of the following claims and their equivalents.
Claims
1. A transistor, comprising:
- a first electrode;
- a first insulating layer positioned over the first electrode;
- a second electrode positioned over the first insulating layer;
- a second insulating layer positioned over the second electrode;
- a semiconductor channel layer extending upwards from the first electrode and passing through the first insulating layer, the second electrode, and the second insulating layer; and
- a third electrode positioned over the second insulating layer and in contact with a top surface of the semiconductor channel layer, wherein the semiconductor channel layer has a sidewall in contact with the first insulating layer, the second electrode, and the second insulating layer, wherein the semiconductor channel layer has a crystal plane with Miller Index (010).
2. (canceled)
3. A transistor, comprising:
- a first electrode;
- a first insulating layer positioned over the first electrode;
- a second electrode positioned over the first insulating layer;
- a second insulating layer positioned over the second electrode;
- a semiconductor channel layer extending upwards from the first electrode and passing through the first insulating layer, the second electrode, and the second insulating layer; and
- a third electrode positioned over the second insulating layer and in contact with a top surface of the semiconductor channel layer, wherein the third electrode includes a hole injection layer and a metal layer on the hole injection layer, wherein the hole injection layer is in contact with the top surface of the semiconductor channel layer.
4. The transistor according to claim 1, wherein the second insulating layer includes an insulating polymer layer and a hard mask layer, wherein the insulating polymer layer is in contact with the second electrode, and the hard mask layer is positioned on the insulating polymer layer.
5. The transistor according to claim 1, wherein the semiconductor channel layer has a height substantially equal to the summed thickness of the first insulating layer, the second electrode and the second insulating layer.
6. A method of manufacturing a transistor, comprising:
- sequentially forming a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer in stack on a substrate;
- patterning the first insulating layer, the second conductive layer, and the second insulating layer to form an opening passing through the first insulating layer, the second conductive layer, and the second insulating layer;
- forming a semiconductor layer over the second insulating layer and filling the opening, wherein the semiconductor layer includes a polymeric semiconductor, and a portion of the semiconductor layer filled in the opening has a crystal plane with Miller Index (010), whereas a portion of the semiconductor layer positioned over the second insulating layer has a crystal plane with Miller Index (100);
- removing a portion of the semiconductor layer positioned over the second insulating layer, wherein a remained portion of the semiconductor layer in the opening form a semiconductor channel; and
- forming a third conductive layer over the semiconductor channel.
7. The method according to claim 6, wherein forming the third conductive layer over the semiconductor channel comprises:
- forming a hole injection layer on the semiconductor channel; and
- forming a metal layer on the hole injection layer.
8. The method according to claim 6, wherein patterning the first insulating layer, the second conductive layer, and the second insulating layer comprises:
- disposing a plurality of particles on the second insulating layer;
- depositing a mask layer covering the particles and the second insulating layer;
- removing the particles and a portion of the mask layer positioned on the particles to form a patterned mask layer on the second insulating layer, wherein the patterned mask layer has a plurality of apertures exposing a portion of the second insulating layer; and
- sequentially etching the second insulating layer, the second conductive layer, and the first insulating layer through the apertures of the patterned mask layer to form the opening passing through the first insulating layer, the second conductive layer, and the second insulating layer.
9. The method according to claim 8, wherein sequentially etching the second insulating layer, the second conductive layer, and the first insulating layer comprises:
- applying a dry etching process to etch the second insulating layer;
- applying a wet etching process to etch the second conductive layer; and
- applying a dry etching process to etch the first insulating layer.
10. (canceled)
Type: Application
Filed: Apr 5, 2017
Publication Date: Mar 15, 2018
Inventors: Hsiao-Wen ZAN (HSINCHU), Shao-Fu PENG (HSINCHU), Cheng-Hang HSU (HSINCHU)
Application Number: 15/480,355