Patents by Inventor Fu Yu

Fu Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250234569
    Abstract: A calabash-shaped MIM capacitor structure includes a stacked layer. The stacked layer includes numerous dielectric layers. An MIM capacitor is disposed within the stacked layer. The MIM capacitor includes a calabash-shaped profile. The calabash-shaped profile includes a rounded bottom, a narrow body and a rounded shoulder disposed from bottom to top.
    Type: Application
    Filed: February 1, 2024
    Publication date: July 17, 2025
    Applicant: United Microelectronics Corp.
    Inventors: Yao-Hsien Chung, Fu-Yu Tsai, Bin-Siang Tsai
  • Publication number: 20250226261
    Abstract: A method of manufacturing a gallium nitride device with field plate structure, including forming a passivation layer covering a substrate and a gate, forming recesses in the passivation layer to define a source region and a drain region, forming a source and a drain on the passivation layer, forming a first ILD layer, a stop layer and a second ILD layer sequentially on the source, the drain and the passivation layer, patterning the first ILD layer, the stop layer and the second ILD layer to form dual-damascene recesses, and filling metal in the dual-damascene recesses to form dual-damascene interconnects connecting respectively with the source and the drain.
    Type: Application
    Filed: March 24, 2025
    Publication date: July 10, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Fu-Yu Tsai, Bin-Siang Tsai, Chung-Yi Chiu
  • Publication number: 20250218693
    Abstract: Disclosed is a capacitor structure including a substrate, a stack structure, and a capacitor. The stack structure includes at least one first dielectric layer and at least one second dielectric layer alternately disposed on the substrate. There is a trench in the at least one first dielectric layer, the at least one second dielectric layer, and the substrate. The trench has at least one recess on at least one sidewall of the at least one first dielectric layer. The capacitor is disposed on a surface of the trench.
    Type: Application
    Filed: February 6, 2024
    Publication date: July 3, 2025
    Applicant: United Microelectronics Corp.
    Inventors: Yao-Hsien Chung, Fu-Yu Tsai, Bin-Siang Tsai
  • Publication number: 20250212424
    Abstract: A semiconductor structure with an MIM capacitor includes a first transistor. The first transistor includes a source and a drain. An interlayer dielectric layer covers the first transistor. A source plug penetrates the interlayer dielectric layer and contacts the source. A drain plug penetrates the interlayer dielectric layer and contacts the drain. A metal interlayer dielectric layer covers the interlayer dielectric layer. An MIM capacitor is disposed in the interlayer dielectric layer and the metal interlayer dielectric layer.
    Type: Application
    Filed: January 10, 2024
    Publication date: June 26, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Bin-Siang Tsai, Fu-Yu Tsai, Chung-Yi Chiu
  • Publication number: 20250212426
    Abstract: A MIM capacitor structure includes a semiconductor substrate, and a first trench and a second trench in the semiconductor substrate in a capacitance forming region. The second trench is adjacent to the first trench. The second trench is deeper than the first trench. A dielectric liner layer conformally covers a top surface of the semiconductor substrate and interior surfaces of the first trench and the second trench. A bottom electrode layer conformally covers the dielectric liner layer. The bottom electrode layer extends onto a top surface of the semiconductor substrate. A capacitor dielectric layer is disposed on the bottom electrode layer in the first trench and the second trench. A top electrode layer is disposed on the capacitor dielectric layer in the first trench and the second trench. The top surface of the top electrode layer is coplanar with the top surface of the bottom electrode layer.
    Type: Application
    Filed: January 10, 2024
    Publication date: June 26, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tai-Cheng Hou, Da-Jun Lin, Bin-Siang Tsai, Fu-Yu Tsai, Ya-Yin Hsiao, Po-Ching Su, Yi-Fan Li, Kuan-Jhih Hou, Yu-Fu Wang, Ti-Bin Chen, Chih-Chiang Wu, Yao-Jhan Wang
  • Patent number: 12329037
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a substrate, forming a first inter-metal dielectric (IMD) layer on the MTJ, removing part of the first IMD layer to form a damaged layer on the MTJ and a trench exposing the damaged layer, performing a ultraviolet (UV) curing process on the damaged layer, and then conducting a planarizing process to remove the damaged layer and part of the first IMD layer.
    Type: Grant
    Filed: December 12, 2021
    Date of Patent: June 10, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tai-Cheng Hou, Chau-Chung Hou, Da-Jun Lin, Wei-Xin Gao, Fu-Yu Tsai, Bin-Siang Tsai
  • Patent number: 12300633
    Abstract: A warpage-reducing semiconductor structure includes a wafer. The wafer includes a front side and a back side. Numerous semiconductor elements are disposed at the front side. A silicon oxide layer is disposed at the back side. A UV-transparent silicon nitride layer covers and contacts the silicon oxide layer. The refractive index of the UV-transparent silicon nitride layer is between 1.55 and 2.10.
    Type: Grant
    Filed: May 9, 2024
    Date of Patent: May 13, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Chin-Chia Yang, Tai-Cheng Hou, Fu-Yu Tsai, Bin-Siang Tsai
  • Patent number: 12293941
    Abstract: A gallium nitride (GaN) device with field plate structure, including a substrate, a gate on the substrate and a passivation layer covering on the gate, a source and a drain on the substrate and the passivation layer, a stop layer on the source, the drain and the passivation layer, and dual-damascene interconnects connecting respectively with the source and the drain, wherein the dual-damascene interconnect is provided with a via portion under the stop layer and a trench portion on the stop layer, and the via portion is connected with the source or the drain, and the trench portion of one of the dual-damascene interconnects extends horizontally toward the drain and overlaps the gate below in vertical direction, thereby functioning as a field plate structure for the GaN device.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: May 6, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Fu-Yu Tsai, Bin-Siang Tsai, Chung-Yi Chiu
  • Publication number: 20250142958
    Abstract: A semiconductor structure includes a SOI substrate having a device layer and a buried oxide layer contiguous with the device layer; a transistor disposed on the device layer; a dielectric layer surrounding the transistor; an interconnect structure disposed on the dielectric layer and electrically connected to a gate of the transistor; a charge trapping layer contiguous with the buried oxide layer; a capping layer contiguous with the charge trapping layer; and a conductive via penetrating through the capping layer, the charge trapping layer, the buried oxide layer, the device layer, and the dielectric layer. The conductive via is electrically connected to the interconnect structure.
    Type: Application
    Filed: December 11, 2023
    Publication date: May 1, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tai-Cheng Hou, Da-Jun Lin, Bin-Siang Tsai, Fu-Yu Tsai
  • Publication number: 20250140666
    Abstract: A semiconductor package includes a RDL interposer having a first surface and a second surface; fanout pads and peripheral pads on the second surface; a first semiconductor die on the first surface and electrically connected to the fanout pads; a molding compound surrounding the first semiconductor die and the first surface of the RDL interposer; through mold vias in the molding compound around the first semiconductor die; peripheral solder bumps within the through mold vias and directly disposed on the peripheral pads; through silicon via pads on the rear surface of the first semiconductor die; a second semiconductor die bonded to the through silicon via pads of the first semiconductor die and the peripheral solder bumps within the through mold vias.
    Type: Application
    Filed: December 14, 2023
    Publication date: May 1, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Bin-Siang Tsai, Fu-Yu Tsai, Tai-Cheng Hou
  • Publication number: 20250132210
    Abstract: A wafer structure includes a substrate having a pre-bonding structure thereon. The pre-bonding structure includes an outer dielectric layer covering a central region of the substrate and a ring-shaped absorbent layer within a ring-shaped peripheral region of the substrate. The ring-shaped absorbent layer is contiguous with the outer dielectric layer.
    Type: Application
    Filed: December 4, 2023
    Publication date: April 24, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yao-Hsien Chung, Tai-Cheng Hou, Chin-Chia Yang, Fu-Yu Tsai, Bin-Siang Tsai
  • Publication number: 20250125252
    Abstract: A semiconductor device includes a device layer, an interlayer dielectric layer disposed above the device layer, a first interconnection structure, a second interconnection structure, and a first dielectric layer. The interlayer dielectric layer includes a first portion and a second portion disposed above a first device region and a second device region, respectively. A top surface of the first portion is lower than a top surface of the second portion in a vertical direction. The first interconnection structure includes first conductive lines partly located in the first portion. The second interconnection structure includes second conductive lines located in the second portion. The first dielectric layer is disposed on the first portion, a part of the first dielectric layer is sandwiched between two adjacent first conductive lines, and a bottom surface of the first dielectric layer is lower than the top surface of the second portion in the vertical direction.
    Type: Application
    Filed: November 21, 2023
    Publication date: April 17, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Chia Yang, Da-Jun Lin, Fu-Yu Tsai, Bin-Siang Tsai
  • Publication number: 20250120092
    Abstract: An MRAM structure includes a first memory unit and a second memory unit. A conductive line is disposed between the first memory unit and the second memory unit. An SOT metal conductive line contacts and electrically connects an end of the first memory unit, an end of the conductive line and an end of the second memory unit. A first switch element is electrically connected to an end of the SOT metal conductive line, and a second switch element is electrically connected to the other end of the SOT metal conductive line. A third switch element is electrically connected to the other end of the first memory unit. A fourth switch element is electrically connected to the other end of the conductive line. A fifth switch element is electrically connected to the other end of the second memory unit.
    Type: Application
    Filed: November 13, 2023
    Publication date: April 10, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Fu-Yu Tsai, Bin-Siang Tsai
  • Publication number: 20250112184
    Abstract: A semiconductor device includes an aluminum (Al) pad on a substrate, a wire bonded onto the Al pad, a cobalt (Co) layer between and directly contacting the Al pad and the wire, and a Co—Pd alloy on the Al pad and divide the Co layer into a first portion, a second portion, and a third portion. Preferably, the wire includes a copper (Cu) wire and a palladium (Pd) layer coated on the Cu wire.
    Type: Application
    Filed: December 13, 2024
    Publication date: April 3, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Bin-Siang Tsai, Fu-Yu Tsai
  • Publication number: 20250113494
    Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.
    Type: Application
    Filed: December 13, 2024
    Publication date: April 3, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Yi-An Shih, Bin-Siang Tsai, Fu-Yu Tsai
  • Patent number: 12256573
    Abstract: A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, a plurality of adhesive rings disposed on the sensor chip, a plurality of filtering lenses respectively adhered to the adhesive rings, and an encapsulant that surrounds the above components. A sensing region of the sensor chip has a layout boundary and a plurality of sub-regions that are defined by the layout boundary and that are separate from each other. The adhesive rings are disposed on the sensing region, and each of the adhesive rings surrounds one of the sub-regions. Each of the filtering lenses, a corresponding one of the adhesive rings, and a corresponding one of the sub-regions jointly define a buffering space. The encapsulant is formed on the substrate and covers the layout boundary of the sensor chip.
    Type: Grant
    Filed: June 6, 2023
    Date of Patent: March 18, 2025
    Assignee: TONG HSING ELECTRONIC INDUSTRIES, LTD.
    Inventors: Chia-Shuai Chang, Chien-Hung Lin, Wen-Fu Yu, Wei-Li Wang, Bae-Yinn Hwang, Jyun-Huei Jiang
  • Patent number: 12254262
    Abstract: A calibration method for emulating a Group III-V semiconductor device, a method for determining trap location within a Group III-V semiconductor device and method for manufacturing a Group III-V semiconductor device are provided. Actual tape-out is performed according to an actual process flow of the Group III-V semiconductor device for manufacturing the Group III-V semiconductor devices and PCM Group III-V semiconductor device. Actual electrical performances of the Group III-V semiconductor devices and the PCM Group III-V semiconductor device are obtained and the actual electrical performances of the Group III-V semiconductor devices and the PCM Group III-V semiconductor device are compared to determine locations where one or more traps appear.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: March 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Chung Chen, Shufang Fu, Kuan-Hung Liu, Chiao-Chun Hsu, Fu-Yu Shih, Chi-Feng Huang, Chu Fu Chen
  • Publication number: 20250086821
    Abstract: This disclosure provides systems, methods, and devices for image signal processing that support eye detection based image frame blending. In a first aspect, a method of image processing includes receiving a plurality of image frames and determining locations for one or more eyes depicted within the image frames. A first image frame may be selected from among the plurality of frames based on the locations of the one or more eyes. And output image frame may be determined by blending at least a subset of the plurality of image frames with the first image frame. In particular implementations, the first image frame may be used as an anchor frame for a multi-frame noise reduction (MFNR) process. Other aspects and features are also claimed and described.
    Type: Application
    Filed: September 13, 2023
    Publication date: March 13, 2025
    Inventors: Fu-Yu Chou, Shih-Jeng Liu
  • Publication number: 20250079293
    Abstract: A semiconductor device and a method of fabricating the same, includes at least one dielectric layer, a conductive structure, and a first insulator. The at least one dielectric layer includes a stacked structure having a low-k dielectric layer, an etching stop layer, and a conductive layer between the low-k dielectric layer and the etching stop layer. The conductive structure is disposed in the first dielectric layer. The first insulator is disposed between the conductive layer and the conductive structure.
    Type: Application
    Filed: October 13, 2023
    Publication date: March 6, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tai-Cheng Hou, Da-Jun Lin, Fu-Yu Tsai, Bin-Siang Tsai
  • Patent number: D1070862
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: April 15, 2025
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Fu-Yu Cai, Chun-Fu Chen, Che-Hsiung Chao, Ming-Chih Huang, Tong-Shen Hsiung, Shang-Chih Liang