Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ, a passivation layer on the first ULK dielectric layer, and a second ULK dielectric layer on the passivation layer.

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.

Abstract: Provided is a low-dose interferon composition for treatment or prevention of conditions, diseases or disorders associated with inflammation in cat. The composition comprises a total concentration of human interferon-?2b in a range of 160 IU/ml to 100,000 IU/ml. The composition is orally administered buccally.

Abstract: Method and devices that include a recessed isolation region in a trench region formed by the removal of a dummy gate structure. The recessed isolation region can allow a greater fin height in the channel region. A metal gate structure may be formed on the recessed isolation region and fin.

Abstract: The present application provides a process for manufacturing an orally disintegrating tablet (ODT) comprising a cytokine as an active pharmaceutical ingredient comprising: acidifying an excipient, conducting a first granulation step of the acidified excipient to obtain acidic powders, and conducting a second granulation step by mixing the acidic powders and the cytokine to obtain granules containing the cytokine. The present application also provides an ODT manufactured by the process.

Abstract: An embodiment includes a semiconductor device, a plurality of fin structures extending from a substrate, the plurality of fin structures having a plurality of first fin structures and a plurality of second fin structures. The semiconductor device also includes a plurality of isolation regions on the substrate and disposed between the plurality of fin structures. The device also includes a plurality of gate structures on the plurality of isolation regions. The device also includes a plurality of epitaxy structures on one of the plurality of first fin structures. The device also includes a plurality of contact structures on the plurality of epitaxy structures, where the plurality of first fin structures, the plurality of gate structures, the plurality of epitaxy structures, and the plurality of contact structures are components of one or more resonators.

Abstract: A method includes: receiving the semiconductor device, wherein the semiconductor device includes: a well region; a doped region; a plurality of gate electrodes; a plurality of source regions; and a plurality of drain regions, wherein the plurality of gate electrodes, the plurality of source region and the plurality of drain regions form a plurality of transistors; and a bulk region disposed in the doped region. A first distance measured between a first transistor of the plurality of transistors and the bulk region is greater than a second distance measured between a second transistor of the plurality of transistors and the bulk region. The method further includes: applying a first voltage to the plurality of drain regions, wherein a first avalanche current generated around the first transistor and shunted through the bulk region is greater than a second avalanche current generated around the second transistor and shunted through the bulk region.

Abstract: A method of making a triple well isolated diode includes growing an epi-layer over a substrate. The method further includes forming a first isolation feature in the epi layer. The method includes implanting a first well in the epi-layer. The method further includes implanting a second well in the epi-layer, wherein a first isolation feature separates a portion of the second well from a portion of the first well. The method further includes implanting a third well in the epi-layer, wherein a sidewall of third well contacts a sidewall of the second well. The method further includes implanting a deep well in the epi-layer, wherein the deep well extends beneath the first well, the deep well extends underneath a first portion of the second well, and a second portion of the second well extends beyond the deep well in a first direction parallel to a top surface of the substrate.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ, a passivation layer on the first ULK dielectric layer, and a second ULK dielectric layer on the passivation layer.

Abstract: The present invention discloses a method of preparing procollagen from freshwater fish. The method comprises the following steps: pressure treatment, physical crushing, mixing and emulsification, homogenization, refrigeration, cleaning, extraction, homogenization, inactivation, homogenization, and filtration. In the mixing and emulsification step, freshwater fish tissue containing collagen is mixed with a surfactant to remove endotoxins to below 0.25 EU/ml. The procollagen is extracted following the step of adding enzymes and an acid solution of pH 3 to 6 to the pretreated tissue. The pretreatment of freshwater fish tissue in this invention can effectively reduce the endotoxins to below 0.25 EU/ml. The extraction technique of this invention can extract and retain greater amounts of procollagen while increasing its denaturation temperature and preserving the intact, tightly twisted triple-helix bonds of type I procollagen.

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.

Abstract: An optical device includes an electronic component, a light-permeable layer, and a ring-shaped adhesive layer that is sandwiched between the electronic component and the light-permeable layer. The ring-shaped adhesive layer surrounds an optical region of the electronic component and includes a plurality of light-weakening slots that are formed on an inner side surface thereof. The light-weakening slots are in a ring-shaped arrangement and surround the optical region. Each of the light-weakening slots has a slot opening having a slot width and a slot bottom spaced apart from the slot opening by a slot depth. A width of each of the light-weakening slots gradually decreases along a direction from the slot opening to the slot bottom, and a ratio of the slot width to the slot depth is within a range from 1:0.86 to 1:11.4, such that each of the light-weakening slots is configured to weaken light irradiated thereon.

Abstract: A semiconductor structure includes a substrate; a first dielectric layer on the substrate; an etch stop layer on the first dielectric layer; a second dielectric layer on the etch stop layer; a first conductor and a second conductor in the second dielectric layer, an air gap in the second dielectric layer and between the first conductor and the second conductor; and a low-polarity dielectric layer on a sidewall surface of the second dielectric layer within the air gap.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a device substrate, a resistance variable layer and a top electrode. The bottom electrode is disposed on the device substrate. The resistance variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance variable layer. The bottom electrode is formed with a tensile stress, while the top electrode is formed with a compressive stress.

Abstract: A warpage-reducing semiconductor structure includes a wafer. The wafer includes a front side and a back side. Numerous semiconductor elements are disposed at the front side. A silicon oxide layer is disposed at the back side. A UV-transparent silicon nitride layer covers and contacts the silicon oxide layer. The refractive index of the UV-transparent silicon nitride layer is between 1.55 and 2.10.

Abstract: A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, a plurality of adhesive rings disposed on the sensor chip, a plurality of filtering lenses respectively adhered to the adhesive rings, and an encapsulant that surrounds the above components. A sensing region of the sensor chip has a layout boundary and a plurality of sub-regions that are defined by the layout boundary and that are separate from each other. The adhesive rings are disposed on the sensing region, and each of the adhesive rings surrounds one of the sub-regions. Each of the filtering lenses, a corresponding one of the adhesive rings, and a corresponding one of the sub-regions jointly define a buffering space. The encapsulant is formed on the substrate and covers the layout boundary of the sensor chip.

Abstract: A method of making a triple well isolated diode includes forming a buried layer in a substrate. The method further includes forming an epi-layer over the substrate and the buried layer. The method further includes forming a first well in the epi-layer, wherein the first well forms an interface with the buried layer. The method further includes forming a second well in the epi-layer surrounding the first well. The method further includes forming a third well in the epi-layer surrounding the second well. The method further includes forming a deep well in the epi-layer beneath the first well to electrically connect to the second well. The method further includes forming a first plurality of isolation features between the first well and the second well. The method further includes forming a second plurality of isolation features between the third well and the epi-layer.