Abstract: A compound semiconductor device includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a passivation layer on the barrier layer, and a contact area recessed into the passivation layer and the barrier layer. The channel layer is partially exposed at a bottom of the contact area. Abi-layer silicide film is disposed on the contact area.

Abstract: The present disclosure is related to a semiconductor device and a fabricating method thereof, and the semiconductor device includes a first dielectric layer and a first conductive structure. The first dielectric layer includes a stacked structure including a low-k dielectric layer, an etching stop layer, and a carbon-rich dielectric layer between the low-k dielectric layer and the etching stop layer, wherein a carbon concentration within the carbon-rich dielectric layer is above 15%. The first conductive structure is disposed in the first dielectric layer.

Abstract: An interposer includes a substrate having an inductor forming region thereon, a plurality of trenches within the inductor forming region in the substrate, a buffer layer lining interior surfaces of the plurality of trenches and forming air gaps within the plurality of trenches, and an inductor coil pattern embedded in the buffer layer within the inductor forming region.

Abstract: A structure of an MIM capacitor and a heat sink include a dielectric layer. The dielectric layer includes a capacitor region and a heat dispensing region. A bottom electrode is embedded in the dielectric layer. A first heat conductive layer covers the dielectric layer. A capacitor dielectric layer is disposed on the first heat conductive layer within the capacitor region. A second heat conductive layer covers and contacts the capacitor dielectric layer and the first heat conductive layer. A top electrode is disposed within the capacitor region and the heat dispensing region and covers the second heat conductive layer. A first heat sink is disposed within the heat dispensing region and contacts the top electrode. A second heat sink is disposed within the heat dispensing region and contacts the first heat conductive layer and the second heat conductive layer.

Abstract: A metal-insulator-metal capacitor includes a bottom electrode, a dielectric layer, a superlattice layer, a silicon dioxide layer and a top electrode stacked from bottom to top. The superlattice layer contacts the dielectric layer. A silicon dioxide layer has a negative voltage coefficient of capacitance.

Abstract: A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, a ring-shaped supporting layer disposed on the sensor chip, and a light-permeable layer disposed on the ring-shaped supporting layer. The ring-shaped supporting layer has an inner surrounding surface and an outer surrounding surface that is opposite to the inner surrounding surface. At least one of the inner surrounding surface and the outer surrounding surface has a plurality of round-ended microstructures that are sequentially connected to each other and that surround a sensing region of the sensor chip. An end of each of the round-ended microstructures is a round-ended portion having a radius of less than 1 ?m. The light-permeable layer, the inner surrounding surface of the ring-shaped supporting layer, and the sensor chip jointly define an enclosed space.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming an aluminum (Al) pad on a substrate, forming a passivation layer on the substrate and an opening exposing the Al pad, forming a cobalt (Co) layer in the opening and on the Al pad, bonding a wire onto the Co layer, and then performing a thermal treatment process to form a Co—Pd alloy on the Al pad.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ, a passivation layer on the first ULK dielectric layer, and a second ULK dielectric layer on the passivation layer.

Abstract: Provided is a low-dose interferon composition for treatment or prevention of conditions, diseases or disorders associated with inflammation in cat. The composition comprises a total concentration of human interferon-?2b in a range of 160 IU/ml to 100,000 IU/ml. The composition is orally administered buccally.

Abstract: The present application provides a process for manufacturing an orally disintegrating tablet (ODT) comprising a cytokine as an active pharmaceutical ingredient comprising: acidifying an excipient, conducting a first granulation step of the acidified excipient to obtain acidic powders, and conducting a second granulation step by mixing the acidic powders and the cytokine to obtain granules containing the cytokine. The present application also provides an ODT manufactured by the process.

Abstract: Method and devices that include a recessed isolation region in a trench region formed by the removal of a dummy gate structure. The recessed isolation region can allow a greater fin height in the channel region. A metal gate structure may be formed on the recessed isolation region and fin.

Abstract: An embodiment includes a semiconductor device, a plurality of fin structures extending from a substrate, the plurality of fin structures having a plurality of first fin structures and a plurality of second fin structures. The semiconductor device also includes a plurality of isolation regions on the substrate and disposed between the plurality of fin structures. The device also includes a plurality of gate structures on the plurality of isolation regions. The device also includes a plurality of epitaxy structures on one of the plurality of first fin structures. The device also includes a plurality of contact structures on the plurality of epitaxy structures, where the plurality of first fin structures, the plurality of gate structures, the plurality of epitaxy structures, and the plurality of contact structures are components of one or more resonators.

Abstract: A method of making a triple well isolated diode includes growing an epi-layer over a substrate. The method further includes forming a first isolation feature in the epi layer. The method includes implanting a first well in the epi-layer. The method further includes implanting a second well in the epi-layer, wherein a first isolation feature separates a portion of the second well from a portion of the first well. The method further includes implanting a third well in the epi-layer, wherein a sidewall of third well contacts a sidewall of the second well. The method further includes implanting a deep well in the epi-layer, wherein the deep well extends beneath the first well, the deep well extends underneath a first portion of the second well, and a second portion of the second well extends beyond the deep well in a first direction parallel to a top surface of the substrate.

Abstract: A method includes: receiving the semiconductor device, wherein the semiconductor device includes: a well region; a doped region; a plurality of gate electrodes; a plurality of source regions; and a plurality of drain regions, wherein the plurality of gate electrodes, the plurality of source region and the plurality of drain regions form a plurality of transistors; and a bulk region disposed in the doped region. A first distance measured between a first transistor of the plurality of transistors and the bulk region is greater than a second distance measured between a second transistor of the plurality of transistors and the bulk region. The method further includes: applying a first voltage to the plurality of drain regions, wherein a first avalanche current generated around the first transistor and shunted through the bulk region is greater than a second avalanche current generated around the second transistor and shunted through the bulk region.

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ, a passivation layer on the first ULK dielectric layer, and a second ULK dielectric layer on the passivation layer.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.

Abstract: The present invention discloses a method of preparing procollagen from freshwater fish. The method comprises the following steps: pressure treatment, physical crushing, mixing and emulsification, homogenization, refrigeration, cleaning, extraction, homogenization, inactivation, homogenization, and filtration. In the mixing and emulsification step, freshwater fish tissue containing collagen is mixed with a surfactant to remove endotoxins to below 0.25 EU/ml. The procollagen is extracted following the step of adding enzymes and an acid solution of pH 3 to 6 to the pretreated tissue. The pretreatment of freshwater fish tissue in this invention can effectively reduce the endotoxins to below 0.25 EU/ml. The extraction technique of this invention can extract and retain greater amounts of procollagen while increasing its denaturation temperature and preserving the intact, tightly twisted triple-helix bonds of type I procollagen.