Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

Abstract: A method of making a triple well isolated diode includes forming a buried layer in a substrate. The method further includes forming an epi-layer over the substrate and the buried layer. The method further includes forming a first well in the epi-layer, wherein the first well forms an interface with the buried layer. The method further includes forming a second well in the epi-layer surrounding the first well. The method further includes forming a third well in the epi-layer surrounding the second well. The method further includes forming a deep well in the epi-layer beneath the first well to electrically connect to the second well. The method further includes forming a first plurality of isolation features between the first well and the second well. The method further includes forming a second plurality of isolation features between the third well and the epi-layer.

Abstract: A triple well isolated diode including a substrate having a first conductivity type and a buried layer in the substrate. The buried layer has a second conductivity type opposite to the first conductivity type. The triple well isolated diode includes an epi-layer over the substrate and the buried layer. A portion of the epi-layer having the first conductivity type contacts the buried layer. The triple well isolated diode includes a first well, a second well, a third well and a deep well in the epi-layer. The first well and the third well have the second conductivity type. The second well and the deep well have the first conductivity type. The second well surrounds sides of the first well. The third well surrounds sides of the second well. The deep well extends beneath the first well to electrically connect to the second well on opposite sides of the first well.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed over the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a field plate formed over the substrate between the gate structure and the drain region; wherein the field plate is coupled to the source region or a bulk electrode of the substrate. An associated method for fabricating the semiconductor structure is also disclosed.

Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed over the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a field plate formed over the substrate between the gate structure and the drain region; wherein the field plate is coupled to the source region or a bulk electrode of the substrate. An associated method for fabricating the semiconductor structure is also disclosed.

Abstract: Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask.

Abstract: A semiconductor device includes a substrate and a gate structure over a top surface of the substrate. The semiconductor device further includes a source in the substrate on a first side of the gate structure. The semiconductor device further includes a drain in the substrate on a second side of the gate structure. The semiconductor device further includes a first well having a first dopant type, wherein the first well surrounds the source. The semiconductor device further includes a second well having a second dopant type opposite the first dopant type, wherein the second well surrounds the drain, an entirety of an upper most surface of the second well between the drain and the first well is coplanar with the top surface of the substrate, and the second well is spaced from the first well.

Abstract: The present disclosure provides a transistor structure, including a self-aligned source-drain structure surrounded by an insulating structure and a gate of a second conductive type separated from the source and the drain by the insulating structure. The self-aligned source-drain structure includes a source and a drain of a first conductive type, a channel between the source and the drain, and a polysilicon contact over and aligned with the channel. A method for manufacturing the transistor structure is also provided in the present disclosure.

Abstract: A metal-oxide-semiconductor field effect transistor (MOSFET) includes a substrate and a gate structure over a top surface of the substrate. The MOSFET further includes a source in the substrate on a first side of the gate structure and a drain in the substrate on a second side of the gate structure opposite the first side. The gate structure includes a variable thickness gate dielectric layer. The variable thickness gate dielectric layer includes a first portion closest to the drain, the first portion having a first thickness. The variable thickness gate dielectric layer further includes a second portion distal from the drain, the second portion having a second thickness less than the first thickness.

Abstract: The present disclosure provides a transistor structure, including a self-aligned source-drain structure surrounded by an insulating structure and a gate of a second conductive type separated from the source and the drain by the insulating structure. The self-aligned source-drain structure includes a source and a drain of a first conductive type, a channel between the source and the drain, and a polysilicon contact over and aligned with the channel. A method for manufacturing the transistor structure is also provided in the present disclosure.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed over the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a field plate formed over the substrate between the gate structure and the drain region; wherein the field plate is coupled to the source region or a bulk electrode of the substrate. An associated method for fabricating the semiconductor structure is also disclosed.

Abstract: Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask.

Abstract: Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask.

Abstract: A metal-oxide-semiconductor field effect transistor (MOSFET) includes a substrate and a gate structure over a top surface of the substrate. The MOSFET further includes a source in the substrate on a first side of the gate structure and a drain in the substrate on a second side of the gate structure opposite the first side. A surface portion of the substrate extending from the source to the drain has an asymmetric dopant concentration profile.

Abstract: A method of forming a manufacture includes forming a trench in a doped layer; and forming a gate dielectric layer along sidewalls of an upper portion of the trench. The method further includes forming a first conductive feature along sidewalls of the gate dielectric layer, wherein the first conductive feature has a first depth in the trench. The method further includes forming an insulating layer covering the first conductive feature and the first insulating layer. The method further includes forming a second conductive feature along sidewalls of the second insulating layer, wherein the second conductive feature has a second depth in the trench different from the first depth.

Abstract: The present disclosure provides an FET structure including a substrate of a first conductive type having a top surface, a first gate over the top surface, a source and a drain of a second conductive type in the substrate, and a first channel under the first gate. A dopant concentration of a first conductive type includes double Gaussian peaks measured less than 200 nm beneath the top surface, from one end of the first gate to the other end of the first gate along the first channel. In some embodiments, the FET structure further including a second gate over the top surface and a second channel under the second gate. A dopant concentration of a first conductive type includes a single Gaussian peak measured less than 200 nm beneath the top surface, from one end of the second gate to the other end of the second gate along the second channel.

Abstract: A triple well isolated diode including a substrate having a first conductivity type and a buried layer in the substrate. The buried layer has a second conductivity type opposite to the first conductivity type. The triple well isolated diode includes an epi-layer over the substrate and the buried layer. A portion of the epi-layer having the first conductivity type contacts the buried layer. The triple well isolated diode includes a first well, a second well, a third well and a deep well in the epi-layer. The first well and the third well have the second conductivity type. The second well and the deep well have the first conductivity type. The second well surrounds sides of the first well. The third well surrounds sides of the second well. The deep well extends beneath the first well to electrically connect to the second well on opposite sides of the first well.

Abstract: A novel MOS transistor, which includes a source region, a drain region, a channel region, an isolation region, a drift region, a gate dielectric layer, a gate electrode and a field plate, is provided. The gate electrode has a first portion and a second portion. The first portion of a first conductivity type is located over the channel region and has a width equal to or greater than a distance of the gate electrode overlapped with the channel region. The second portion is un-doped and located over the isolation region. Accordingly, the MOS transistor allows higher process freedom saves production cost, as well as improves reliability.

Abstract: A novel MOS transistor including a well region, a gate dielectric layer, a gate electrode, a source region and a drain region is provided. The well region of a first conductivity type extends into a semiconductor substrate. The gate dielectric layer is located over the well region. The gate electrode is located over the gate dielectric layer. The source region of a second conductivity type opposite to the first conductivity type and a drain region of the second conductivity type are located in the well region and on opposite sides of the gate electrode. The gate dielectric layer has a first portion and a second portion respectively closest to the source region and the drain region. The thickness of the second portion is greater than that of the first portion, so as to raise breakdown voltage and to maintain current simultaneously.