Patents by Inventor Fuad Badrieh

Fuad Badrieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10170448
    Abstract: Apparatuses for supplying power supply voltage in a plurality of dies are described. An example apparatus includes: a circuit board; a regulator on the circuit board that regulates a first voltage; a semiconductor device on the circuit board that receives the first voltage through a power line in the circuit board. The semiconductor device includes: a substrate on the circuit board, stacked via conductive balls, that receives the first voltage from the power line via the conductive balls; a plurality of dies on the semiconductor device, stacked via bumps, each die including a first conductive via that receives the first voltage via the bumps; a plurality of pillars between adjacent dies and couple the first conductive vias of the adjacent dies; and a sense node switch circuit that selectively couples one first conductive via of one die among the plurality of dies to the regulator.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: January 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Adam S. El-Mansouri, Fuad Badrieh, Brent Keeth
  • Publication number: 20180158800
    Abstract: Apparatuses for supplying power supply voltage in a plurality of dies are described. An example apparatus includes: a circuit board; a regulator on the circuit board that regulates a first voltage; a semiconductor device on the circuit board that receives the first voltage through a power line in the circuit board. The semiconductor device includes: a substrate on the circuit board, stacked via conductive balls, that receives the first voltage from the power line via the conductive balls; a plurality of dies on the semiconductor device, stacked via bumps, each die including a first conductive via that receives the first voltage via the bumps; a plurality of pillars between adjacent dies and couple the first conductive vias of the adjacent dies; and a sense node switch circuit that selectively couples one first conductive via of one die among the plurality of dies to the regulator.
    Type: Application
    Filed: December 7, 2016
    Publication date: June 7, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Adam S. El-Mansouri, Fuad Badrieh, Brent Keeth
  • Patent number: 7166902
    Abstract: In one embodiment, an electrically conductive trench in an integrated circuit allows for the formation of capacitors between the trench and other portions of the integrated circuit. For example, a capacitor may be formed between the trench and an electrically conductive line. Among other advantages, the capacitor provides a relatively large capacitance while occupying a relatively small area.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: January 23, 2007
    Assignee: Cypress Semiconductor Corporation
    Inventors: Fuad Badrieh, Feng Dai, Bartosz Banachowicz, Roger J. Bettman
  • Patent number: 7018942
    Abstract: In one embodiment, a passivation level includes a low-k dielectric. The low-k dielectric helps lower the capacitance of a metal line in a last metal level, which may be just below the passivation level. In another embodiment, the metal line is relatively thick. This helps lower the metal line's resistance and resulting RC delay.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: March 28, 2006
    Assignee: Cypress Semiconductor Corporation
    Inventors: Mira Ben-Tzur, Krishnaswamy Ramkumar, Alain Blosse, Fuad Badrieh
  • Patent number: 6841878
    Abstract: In one embodiment, a passivation level includes a low-k dielectric. The low-k dielectric helps lower the capacitance of a metal line in a last metal level, which may be just below the passivation level. In another embodiment, the metal line is relatively thick. This helps lower the metal line's resistance and resulting RC delay.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: January 11, 2005
    Assignee: Cypress Semiconductor Corporation
    Inventors: Mira Ben-Tzur, Krishnaswamy Ramkumar, Alain Blosse, Fuad Badrieh
  • Patent number: 6660661
    Abstract: In one embodiment, a passivation level includes a low-k dielectric. The low-k dielectric helps lower the capacitance of a metal line in a last metal level, which may be just below the passivation level. In another embodiment, the metal line is relatively thick. This helps lower the metal line's resistance and resulting RC delay.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: December 9, 2003
    Assignee: Cypress Semiconductor Corporation
    Inventors: Mira Ben-Tzur, Krishnaswamy Ramkumar, Alain Blosse, Fuad Badrieh