Abstract: In an electronic device with a serial ATA interface, upon detection of the issue or reception of a preset command, a confirmation device, such as a CPU, confirms the completion of execution of the command. Upon confirming the completion of execution of the command, a controller, which may also be the CPU, controls shifting of the serial ATA interface to a power saving mode.

Abstract: In an electronic device with a serial ATA interface, upon detection of the issue or reception of a preset command, a confirmation device, such as a CPU, confirms the completion of execution of the command. Upon confirming the completion of execution of the command, a controller, which may also be the CPU, controls shifting of the serial ATA interface to a power saving mode.

Abstract: In an electronic device with a serial ATA interface, upon detection of the issue or reception of a preset command, a confirmation device, such as a CPU, confirms the completion of execution of the command. Upon confirming the completion of execution of the command, a controller, which may also be the CPU, controls shifting of the serial ATA interface to a power saving mode.

Abstract: In an electronic device with a serial ATA interface, upon detection of the issue or reception of a preset command, a confirmation device, such as a CPU, confirms the completion of execution of the command. Upon confirming the completion of execution of the command, a controller, which may also be the CPU, controls shifting of the serial ATA interface to a power saving mode.

Abstract: In an electronic device with a serial ATA interface, upon detection of the issue or reception of a preset command, a confirmation device, such as a CPU, confirms the completion of execution of the command. Upon confirming the completion of execution of the command, a controller, which may also be the CPU, controls shifting of the serial ATA interface to a power saving mode.

Abstract: In an electronic device with a serial ATA interface, upon detection of the issue or reception of a preset command, a confirmation device, such as a CPU, confirms the completion of execution of the command. Upon confirming the completion of execution of the command, a controller, which may also be the CPU, controls shifting of the serial ATA interface to a power saving mode.

Abstract: An electronic device has a serial ATA interface and an inhibition-signal generator. The serial ATA interface transmits data to another electronic device with a serial ATA interface connected thereto via a bus. The inhibition-signal generator is configured to generate an inhibition signal to inhibit at least one of a restoration request and a power saving request. The restoration request has the function of requesting the other electronic device to restore its serial ATA interface from a power-saving state to the non power-saving state. The power saving request is supplied from the other electronic device to the electronic device for requesting the serial ATA interface of the electronic device to shift to a power-saving state from a non power saving state.

Abstract: In an electronic device with a serial ATA interface, upon detection of the issue or reception of a preset command, a confirmation device, such as a CPU, confirms the completion of execution of the command. Upon confirming the completion of execution of the command, a controller, which may also be the CPU, controls shifting of the serial ATA interface to a power saving mode.

Abstract: An HDC has first and second terminals. The first terminal is used to output a first write gate signal that dictates writing of data to the disk. The second terminal is used to input a second write gate signal output from an external circuit. The external circuit performs predetermined signal processing on write data in accordance with the first write gate signal output from the first terminal, and outputs the second write gate signal that reflects a signal delay in the circuit. A write inhibition controller incorporated in the HDC monitors the second write gate signal input via the second terminal, and detects, as a write inhibition state, a state in which writing of data to the disk is dictated during a period in which writing of data to the disk should be inhibited.

Abstract: The CPU of an electronic device generates a parameter for determining the amplitude of a serial data signal when it is output from an output device to a serial ATA bus. The parameter indicates a value that is needed to make the amplitude of the received serial data signal fall within a range, stipulated in serial ATA interface standards, when another electronic device receives the serial data signal. The parameter is generated in accordance with the cable length of the serial ATA bus designated by a cable length designation unit. The other electronic device is connected to the serial ATA bus.

Abstract: An electronic device has a serial ATA interface and an inhibition-signal generator. The serial ATA interface transmits data to another electronic device with a serial ATA interface connected thereto via a bus. The inhibition-signal generator is configured to generate an inhibition signal to inhibit at least one of a restoration request and a power saving request. The restoration request has the function of requesting the other electronic device to restore its serial ATA interface from a power-saving state to the non power-saving state. The power saving request is supplied from the other electronic device to the electronic device for requesting the serial ATA interface of the electronic device to shift to a power-saving state from a non power saving state.

Abstract: In an electronic device with a serial ATA interface, upon detection of the issue or reception of a preset command, a confirmation device, such as a CPU, confirms the completion of execution of the command. Upon confirming the completion of execution of the command, a controller, which may also be the CPU, controls shifting of the serial ATA interface to a power saving mode.

Abstract: An electronic device has a serial ATA interface and is connected to another electronic device through that serial ATA bus. A determination device determines whether immediate transmission of data is possible when the data should be transmitted to the another electronic device. A first mode switching device switches the serial ATA bus from a non power saving mode to a specific power saving mode when the immediate transmission of the data from the electronic device is determined to be impossible and the data is predicted as not being prepared within a preset time. A second mode switching device switches the serial ATA bus from the specific power saving mode to the non power saving mode after preparations are made for transmission of the data where the serial ATA bus is switched to the specific power saving mode.

Abstract: The CPU of an electronic device generates a parameter for determining the amplitude of a serial data signal when it is output from an output device to a serial ATA bus. The parameter indicates a value that is needed to make the amplitude of the received serial data signal fall within a range, stipulated in serial ATA interface standards, when another electronic device receives the serial data signal. The parameter is generated in accordance with the cable length of the serial ATA bus designated by a cable length designation unit. The other electronic device is connected to the serial ATA bus.

Abstract: An amplitude detector incorporated in an electronic device with a serial ATA interface detects the amplitude of a serial data signal input to an I/O circuit via a SATA bus. An averaging unit averages the detection results of the amplitude detector. A comparator compares the resultant average with an expected input signal amplitude. Based on the comparison result, an amplitude adjuster adjusts the amplitude of a serial data signal when this signal is output from the I/O circuit. Adjustment is performed such that when the serial data signal output from the I/O circuit is input to another electronic device via the SATA bus, it has an amplitude at least approximately equal to the expected input signal amplitude. In other embodiments, the invention utilizes an amplitude detector, comparator and adjuster and employs a step-by-step adjustment of the electronic device with another similarly equipped electronic device.

Abstract: An HDC has first and second terminals. The first terminal is used to output a first write gate signal that dictates writing of data to the disk. The second terminal is used to input a second write gate signal output from an external circuit. The external circuit performs predetermined signal processing on write data in accordance with the first write gate signal output from the first terminal, and outputs the second write gate signal that reflects a signal delay in the circuit. A write inhibition controller incorporated in the HDC monitors the second write gate signal input via the second terminal, and detects, as a write inhibition state, a state in which writing of data to the disk is dictated during a period in which writing of data to the disk should be inhibited.

Abstract: A disclosed disk drive has a disk assigned with a plurality of hidden storage areas. The disk drive includes an authentication module which performs authentication processing for each hidden storage area in response to an access request from a host system. The authentication module exchanges information with the host system and performs authentication processing to determine access permission for each hidden storage area by using key information and unique information defined for each hidden storage area.

Abstract: Disclosed herein is a system for controlling the process of performing a command in an HDD. The HDD comprises a register for holding the command control information supplied from a host system, a command register for holding a specific command. The HDD further comprises a CPU. The CPU fetches the command control information from the register when the specific command held in the command register is one for setting the command control information. The CPU controls the process of performing a command in accordance with the command control information, thereby to finish performing the command within a period between the time when the host system issued the command and the time when the host system issues the next command.

Abstract: A disclosed disk drive has a disk assigned with a plurality of hidden storage areas. The disk drive includes an authentication module which performs authentication processing for each hidden storage area in response to an access request from a host system. The authentication module exchanges information with the host system and performs authentication processing to determine access permission for each hidden storage area by using key information and unique information defined for each hidden storage area.

Abstract: A disk drive capable of setting a hidden area in which the access thereto is limited, on a disk is disclosed. The disk drive sets a predetermined storage area on the disk as a hidden area in accordance with a setting command from a host system. In accordance with this setting processing, the disk drive informs the host system of a capacity of a normal storage area comprising all storage areas on the disk except for the hidden area. Further, the disk drive cancels the hidden area on the disk and changes it to the normal storage area in accordance with a canceling command from the host system. In accordance with this canceling command, the disk drive erases the data, which is recorded in the hidden area on the disk.