Patents by Inventor Fuchao Wang

Fuchao Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10654714
    Abstract: An integrated semiconductor heating assembly includes a semiconductor substrate, a chamber formed therein, and an exit port in fluid communication with the chamber, allowing fluid to exit the chamber in response to heating the chamber. The integrated heating assembly includes a first heating element adjacent the chamber, which can generate heat above a selected threshold and bias fluid in the chamber toward the exit port. A second heating element is positioned adjacent the exit port to generate heat above a selected threshold, facilitating movement of the fluid through the exit port away from the chamber. Addition of the second heating element reduces the amount of heat emitted per heating element and minimizes thickness of a heat absorption material toward an open end of the exit port. Since such material is expensive, this reduces the manufacturing cost and retail price of the assembly while improving efficiency and longevity thereof.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: May 19, 2020
    Assignee: STMicroelectronics, Inc.
    Inventors: Ming Fang, Fuchao Wang
  • Publication number: 20190341181
    Abstract: An integrated magnetic device has a magnetic core which includes layers of the magnetic material located in a trench in a dielectric layer. The magnetic material layers are flat and parallel to a bottom of the trench, and do not extend upward along sides of the trench. The integrated magnetic device is formed by forming layers of the magnetic material over the dielectric layer and extending into the trench. A protective layer is formed over the magnetic material layers. The magnetic material layers are removed from over the dielectric layer, leaving the magnetic material layers and a portion of the protective layer in the trench. The magnetic material layers along sides of the trench are subsequently removed. The magnetic material layers along the bottom of the trench provide the magnetic core.
    Type: Application
    Filed: July 16, 2019
    Publication date: November 7, 2019
    Inventors: Fuchao Wang, Yousong Zhang, Neal Thomas Murphy, Brian Zinn, Jonathan P. Davis
  • Patent number: 10403424
    Abstract: An integrated magnetic device has a magnetic core which includes layers of the magnetic material located in a trench in a dielectric layer. The magnetic material layers are flat and parallel to a bottom of the trench, and do not extend upward along sides of the trench. The integrated magnetic device is formed by forming layers of the magnetic material over the dielectric layer and extending into the trench. A protective layer is formed over the magnetic material layers. The magnetic material layers are removed from over the dielectric layer, leaving the magnetic material layers and a portion of the protective layer in the trench. The magnetic material layers along sides of the trench are subsequently removed. The magnetic material layers along the bottom of the trench provide the magnetic core.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: September 3, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Fuchao Wang, Yousong Zhang, Neal Thomas Murphy, Brian Zinn, Jonathan P. Davis
  • Publication number: 20190141789
    Abstract: An integrated circuit is provided having an active circuit. A heating element is adjacent to the active circuit and configured to heat the active circuit. A temperature sensor is also adjacent to the active circuit and configured to measure a temperature of the active circuit. A temperature controller is coupled to the active circuit and configured to receive a temperature signal from the temperature sensor. The temperature controller operates the heating element to heat the active circuit to maintain the temperature of the active circuit in a selected temperature range.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 9, 2019
    Inventors: Fuchao WANG, Olivier LENEEL, Ravi SHANKAR
  • Patent number: 10276787
    Abstract: An integrated device includes a substrate having a semiconductor surface layer including functional circuitry, a lower metal stack on the semiconductor surface layer, an interlevel dielectric (ILD) layer on the lower metal stack, a top metal layer providing AMR contact pads and bond pads coupled to the AMR contact pads in the ILD layer. An AMR device is above the lower metal stack lateral to the functional circuitry including a patterned AMR stack including a seed layer, an AMR material layer, and a capping layer, wherein the seed layer is coupled to the AMR contact pads by a coupling structure. A protective overcoat (PO layer) is over the AMR stack. There are openings in the PO layer exposing the bond pads.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: April 30, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dok Won Lee, William David French, Ricky Alan Jackson, Fuchao Wang
  • Patent number: 10230273
    Abstract: An electricity transmission sending device includes: a transmission circuit and a coil, where the transmission circuit includes a signal sending unit and a controlling unit, and the coil includes at least two mutually perpendicular subcoils. The signal sending unit is configured to receive a required power signal and an actually received power signal that are sent by the electricity transmission receiving device; and the controlling unit is configured to adjust a magnetic field direction in which wireless electricity transmission to the electricity transmission receiving device is performed and control the coil to transmit electric energy to the electricity transmission receiving device in an optimal magnetic field direction, where the optimal magnetic field direction refers to a corresponding magnetic field direction when a power value of electric energy actually received by the electricity transmission receiving device is maximum in a case of specific output power of the coil.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: March 12, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Fuchao Wang, Fan Tian, Yuchao Zhang
  • Patent number: 10206247
    Abstract: An integrated circuit is provided having an active circuit. A heating element is adjacent to the active circuit and configured to heat the active circuit. A temperature sensor is also adjacent to the active circuit and configured to measure a temperature of the active circuit. A temperature controller is coupled to the active circuit and configured to receive a temperature signal from the temperature sensor. The temperature controller operates the heating element to heat the active circuit to maintain the temperature of the active circuit in a selected temperature range.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: February 12, 2019
    Assignees: STMICROELECTRONICS, INC., STMICROELECTRONICS ASIA PACIFIC PTE LTD
    Inventors: Fuchao Wang, Olivier Le Neel, Ravi Shankar
  • Publication number: 20180358163
    Abstract: An integrated magnetic device has a magnetic core which includes layers of the magnetic material located in a trench in a dielectric layer. The magnetic material layers are flat and parallel to a bottom of the trench, and do not extend upward along sides of the trench. The integrated magnetic device is formed by forming layers of the magnetic material over the dielectric layer and extending into the trench. A protective layer is formed over the magnetic material layers. The magnetic material layers are removed from over the dielectric layer, leaving the magnetic material layers and a portion of the protective layer in the trench. The magnetic material layers along sides of the trench are subsequently removed. The magnetic material layers along the bottom of the trench provide the magnetic core.
    Type: Application
    Filed: June 9, 2017
    Publication date: December 13, 2018
    Applicant: Texas Instruments Incorporated
    Inventors: Fuchao Wang, Yousong Zhang, Neal Thomas Murphy, Brian Zinn, Jonathan P. Davis
  • Patent number: 10068769
    Abstract: In a described example method, semiconductor wafer with a backside silicon nitride layer is encapsulated with a diffusion barrier layer prior to a high temperature anneal greater than about 1000 degrees Celsius. After the high temperature anneal the diffusion barrier layer and the backside silicon nitride layers are stripped.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: September 4, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Prakash Dalpatbhai Dev, Fuchao Wang, Nicholas Andrew Kusek
  • Publication number: 20180166280
    Abstract: In a described example method, semiconductor wafer with a backside silicon nitride layer is encapsulated with a diffusion barrier layer prior to a high temperature anneal greater than about 1000 degrees Celsius. After the high temperature anneal the diffusion barrier layer and the backside silicon nitride layers are stripped.
    Type: Application
    Filed: December 14, 2016
    Publication date: June 14, 2018
    Inventors: Prakash Dalpatbhai Dev, Fuchao Wang, Nicholas Andrew Kusek
  • Patent number: 9899334
    Abstract: A method includes: growing a oxide layer on a topside of a semiconductor wafer using a local oxidation of silicon (LOCOS) process; forming a photoresist pattern with an alignment opening on the oxide layer; etching the oxide layer to form a trench in the oxide layer; etching an alignment mark trench into the exposed surface of the semiconductor wafer; depositing a dielectric layer that is one of a silicon nitride material or a silicon oxynitride material; performing an anisotropic plasma etch to remove the dielectric layer from horizontal surfaces on the oxide layer and the alignment mark trench and to form sidewalls from the dielectric layer on vertical sidewalls of the alignment mark trench; growing an alignment mark oxide layer on a bottom surface of the alignment trench; and etching and removing the oxide layer and the alignment mark oxide layer.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: February 20, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Fuchao Wang, Prakash Dalpatbhai Dev, Dina Rodriguez, Dongping Zhang, Billy Alan Wofford
  • Patent number: 9842895
    Abstract: An integrated circuit contains a thin film resistor in which a body of the thin film resistor is disposed over a lower dielectric layer in a system of interconnects in the integrated circuit. Heads of the thin film resistor are disposed over electrodes which are interconnect elements in the lower dielectric layer, which provide electrical connections to a bottom surface of the thin film resistor. Top surfaces of the electrodes are substantially coplanar with a top surface of the lower dielectric layer. A top surface of the thin film resistor is free of electrical connections. An upper dielectric layer is disposed over the thin film resistor.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: December 12, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pinghai Hao, Fuchao Wang, Duofeng Yue
  • Publication number: 20170236998
    Abstract: An integrated device includes a substrate having a semiconductor surface layer including functional circuitry, a lower metal stack on the semiconductor surface layer, an interlevel dielectric (ILD) layer on the lower metal stack, a top metal layer providing AMR contact pads and bond pads coupled to the AMR contact pads in the ILD layer. An AMR device is above the lower metal stack lateral to the functional circuitry including a patterned AMR stack including a seed layer, an AMR material layer, and a capping layer, wherein the seed layer is coupled to the AMR contact pads by a coupling structure. A protective overcoat (PO layer) is over the AMR stack. There are openings in the PO layer exposing the bond pads.
    Type: Application
    Filed: February 11, 2016
    Publication date: August 17, 2017
    Inventors: DOK WON LEE, WILLIAM DAVID FRENCH, RICKY ALAN JACKSON, FUCHAO WANG
  • Publication number: 20160347610
    Abstract: An integrated semiconductor heating assembly includes a semiconductor substrate, a chamber formed therein, and an exit port in fluid communication with the chamber, allowing fluid to exit the chamber in response to heating the chamber. The integrated heating assembly includes a first heating element adjacent the chamber, which can generate heat above a selected threshold and bias fluid in the chamber toward the exit port. A second heating element is positioned adjacent the exit port to generate heat above a selected threshold, facilitating movement of the fluid through the exit port away from the chamber. Addition of the second heating element reduces the amount of heat emitted per heating element and minimizes thickness of a heat absorption material toward an open end of the exit port. Since such material is expensive, this reduces the manufacturing cost and retail price of the assembly while improving efficiency and longevity thereof.
    Type: Application
    Filed: August 11, 2016
    Publication date: December 1, 2016
    Inventors: Ming FANG, Fuchao WANG
  • Patent number: 9443801
    Abstract: Methods of fabricating a multi-layer semiconductor structure are provided. In one embodiment, a method includes depositing a first dielectric layer over a semiconductor structure, depositing a first metal layer over the first dielectric layer, patterning the first metal layer to form a plurality of first metal lines, and depositing a second dielectric layer over the first metal lines and the first dielectric layer. The method also includes removing a portion of the second dielectric layer over selected first metal lines to expose a respective top surface of each of the selected first metal lines. The method further includes reducing a thickness of the selected first metal lines to be less than a thickness of the unselected first metal lines. A multi-layer semiconductor structure is also provided.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: September 13, 2016
    Assignee: STMicroelectronics, Inc.
    Inventors: Hai Ding, Fuchao Wang, Zhiyong Xie
  • Patent number: 9434166
    Abstract: An integrated semiconductor heating assembly includes a semiconductor substrate, a chamber formed therein, and an exit port in fluid communication with the chamber, allowing fluid to exit the chamber in response to heating the chamber. The integrated heating assembly includes a first heating element adjacent the chamber, which can generate heat above a selected threshold and bias fluid in the chamber toward the exit port. A second heating element is positioned adjacent the exit port to generate heat above a selected threshold, facilitating movement of the fluid through the exit port away from the chamber. Addition of the second heating element reduces the amount of heat emitted per heating element and minimizes thickness of a heat absorption material toward an open end of the exit port. Since such material is expensive, this reduces the manufacturing cost and retail price of the assembly while improving efficiency and longevity thereof.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: September 6, 2016
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Ming Fang, Fuchao Wang
  • Publication number: 20160197135
    Abstract: An integrated circuit contains a thin film resistor in which a body of the thin film resistor is disposed over a lower dielectric layer in a system of interconnects in the integrated circuit. Heads of the thin film resistor are disposed over electrodes which are interconnect elements in the lower dielectric layer, which provide electrical connections to a bottom surface of the thin film resistor. Top surfaces of the electrodes are substantially coplanar with a top surface of the lower dielectric layer. A top surface of the thin film resistor is free of electrical connections. An upper dielectric layer is disposed over the thin film resistor.
    Type: Application
    Filed: February 29, 2016
    Publication date: July 7, 2016
    Inventors: Pinghai HAO, Fuchao WANG, Duofeng YUE
  • Publication number: 20160107533
    Abstract: A mains supply method, including, upon a mains failure, detecting whether a quantity of remaining electricity of the backup mains supply system is not enough for supporting a critical load of the mains supply system to work properly for a time T; if yes, detecting whether a quantity of feedable electricity of an electric vehicle of the mains supply system is greater than zero; and if yes, controlling one or more electric vehicles that can provide feedable electricity and the backup mains supply system to jointly supply electricity to the critical load. Technical solutions provided in the embodiments of the present disclosure can keep, upon the mains failure, the critical load working as long as possible to wait for the mains to restore, that is, can improve working stability of the critical load.
    Type: Application
    Filed: December 28, 2015
    Publication date: April 21, 2016
    Inventors: Bing Cai, Fuchao Wang
  • Patent number: 9305688
    Abstract: An integrated circuit contains a thin film resistor in which a body of the thin film resistor is disposed over a lower dielectric layer in a system of interconnects in the integrated circuit. Heads of the thin film resistor are disposed over electrodes which are interconnect elements in the lower dielectric layer, which provide electrical connections to a bottom surface of the thin film resistor. Top surfaces of the electrodes are substantially coplanar with a top surface of the lower dielectric layer. A top surface of the thin film resistor is free of electrical connections. An upper dielectric layer is disposed over the thin film resistor.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: April 5, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: PingHai Hao, Fuchao Wang, Duofeng Yue
  • Publication number: 20160014845
    Abstract: An integrated circuit is provided having an active circuit. A heating element is adjacent to the active circuit and configured to heat the active circuit. A temperature sensor is also adjacent to the active circuit and configured to measure a temperature of the active circuit. A temperature controller is coupled to the active circuit and configured to receive a temperature signal from the temperature sensor. The temperature controller operates the heating element to heat the active circuit to maintain the temperature of the active circuit in a selected temperature range.
    Type: Application
    Filed: September 16, 2015
    Publication date: January 14, 2016
    Inventors: Fuchao WANG, Olivier LE NEEL, Ravi SHANKAR