Patents by Inventor Fulvio Spagna
Fulvio Spagna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190303342Abstract: An interface couples a controller to a physical layer (PHY) block, where the interface includes a set of data pins comprising transmit data pins to send data to the PHY block and receive data pins to receive data from the PHY block. The interface further includes a particular set of pins to implement a message bus interface, where the controller is to send a write command to the PHY block over the message bus interface to write a value to at least one particular bit of a PHY message bus register, bits of the PHY message bus register are mapped to a set of control and status signals, and the particular bit is mapped to a recalibration request signal to request that the PHY block perform a recalibration.Type: ApplicationFiled: June 19, 2019Publication date: October 3, 2019Applicant: Intel CorporationInventors: Michelle C. Jen, Minxi Gao, Debendra Das Sharma, Fulvio Spagna, Bruce A. Tennant, Noam Dolev Geldbard
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Patent number: 10380046Abstract: Re-initialization of a link can take place without termination of the link, where the link includes, a transmitter and a receiver are to be coupled to each lane in the number of lanes, and re-initialization of the link is to include transmission of a pre-defined sequence on each of the lanes.Type: GrantFiled: March 12, 2018Date of Patent: August 13, 2019Assignee: Intel CorporationInventors: Venkatraman Iyer, Darren S. Jue, Robert G. Blankenship, Fulvio Spagna, Ashish Gupta
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Patent number: 10374616Abstract: Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.Type: GrantFiled: May 29, 2018Date of Patent: August 6, 2019Assignee: Intel CorporationInventors: Wenyan Vivian Jia, Shenggao Li, Fulvio Spagna
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Patent number: 10284210Abstract: Embodiments include apparatuses, methods, and systems for open-loop voltage regulation and drift compensation for a digitally controlled oscillator (DCO). In embodiments, a communication circuit may include a DCO, an open-loop voltage regulator, and a calibration circuit. The open-loop voltage regulator may receive a calibration voltage and may generate a regulated voltage. The regulated voltage may be passed to the DCO. During a calibration mode, the calibration circuit may compare the regulated voltage to a reference voltage and adjust the calibration voltage based on the comparison to provide the regulated voltage with a target value. During a monitoring mode, the calibration circuit may receive a tuning code that is used to tune the DCO and further adjust the calibration voltage based on a value of the tuning code.Type: GrantFiled: August 26, 2016Date of Patent: May 7, 2019Assignee: INTEL CORPORATIONInventors: Shenggao Li, Guluke Tong, Sujatha B. Gowder, Fulvio Spagna
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Patent number: 10248591Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.Type: GrantFiled: December 28, 2016Date of Patent: April 2, 2019Assignee: Intel CorporationInventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert H. Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
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Publication number: 20180375520Abstract: Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.Type: ApplicationFiled: May 29, 2018Publication date: December 27, 2018Inventors: Wenyan Vivian Jia, Shenggao Li, Fulvio Spagna
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Patent number: 10146733Abstract: A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link.Type: GrantFiled: May 27, 2016Date of Patent: December 4, 2018Assignee: Intel CorporationInventors: Venkatraman Iyer, Darren S. Jue, Robert G. Blankenship, Fulvio Spagna, Debendra Das Sharma, Jeffrey C. Swanson
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Publication number: 20180267850Abstract: There is disclosed in an example an interconnect apparatus having: a root circuit; and a downstream circuit comprising at least one receiver; wherein the root circuit is operable to provide a margin test directive to the downstream circuit during a normal operating state; and the downstream circuit is operable to perform a margin test and provide a result report of the margin test to the root circuit. This may be performed in-band, for example in the L0 state. There is also disclosed a system comprising such an interconnect, and a method of performing margin testing.Type: ApplicationFiled: September 26, 2015Publication date: September 20, 2018Inventors: Daniel S. Froelich, Debendra Das Sharma, Fulvio Spagna, Per E. Fornberg, David Edward Bradley
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Publication number: 20180203811Abstract: Re-initialization of a link can take place without termination of the link, where the link includes, a transmitter and a receiver are to be coupled to each lane in the number of lanes, and re-initialization of the link is to include transmission of a pre-defined sequence on cach of the lanes.Type: ApplicationFiled: March 12, 2018Publication date: July 19, 2018Inventors: Venkatraman Iyer, Darren S. Jue, Robert G. Blankenship, Fulvio Spagna, Ashish Gupta
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Publication number: 20180191523Abstract: An apparatus includes an agent to facilitate communication in one of two or more modes, where a first of the two or more modes involves communication over links including a first number of lanes and a second of the two or more modes involves communication over links including a second number of lanes, and the first number is greater than the second number. The apparatus further includes a memory including data to indicate which of the two or modes applies to a particular link and a multiplexer to reverse lane numbering on links including either the first number of lanes or the second number of lanes.Type: ApplicationFiled: December 29, 2016Publication date: July 5, 2018Inventors: Rahul R. Shah, William R. Halleck, Fulvio Spagna, Venkatraman Iyer
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Patent number: 9985637Abstract: Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.Type: GrantFiled: December 27, 2016Date of Patent: May 29, 2018Assignee: Intel CorporationInventors: Wenyan Vivian Jia, Shenggao Li, Fulvio Spagna
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Patent number: 9916266Abstract: Re-initialization of a link can take place without termination of the link, where the link includes, a transmitter and a receiver are to be coupled to each lane in the number of lanes, and re-initialization of the link is to include transmission of a pre-defined sequence on each of the lanes.Type: GrantFiled: August 15, 2016Date of Patent: March 13, 2018Assignee: Intel CorporationInventors: Venkatraman Iyer, Darren S. Jue, Robert G. Blankenship, Fulvio Spagna, Ashish Gupta
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Publication number: 20180006847Abstract: Some embodiments include apparatus and methods using an input unit including a first transistor to receive a first signal of a differential signal pair, a second transistor to receive a second signal of the differential signal pair, and a third transistor to receive a clock signal, with the third transistor coupled to the first and second transistors at a node. The input unit includes a circuit component to form a first circuit path between the node and a supply node during a first phase of the clock signal. The third transistor is to form a second circuit path between the node and the supply node during a second phase of the clock signal. The apparatus includes an output unit coupled to the first and second transistors to generate output information based on voltages of the first and second signals during the second phase of the clock signal.Type: ApplicationFiled: June 30, 2016Publication date: January 4, 2018Inventors: Wenyan Vivian Jia, Ji Chen, Shenggao Li, Fulvio Spagna, Xiaoqing Wang
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Patent number: 9692589Abstract: A redriver is provided that includes a receiver to receive a signal from a first device that includes a portion of a defined binary sequence, a drift buffer to retime the binary sequence and provide a seed to a linear feedback shift register (LFSR) from the binary sequence, the LFSR to generate an expected version of the binary sequence from the seed, and pattern checking logic to compare a sequence in subsequent signals received from the first device with the expected version of the binary sequence generated by the LFSR.Type: GrantFiled: September 26, 2015Date of Patent: June 27, 2017Assignee: Intel CorporationInventors: Venkatraman Iyer, Fulvio Spagna, Debendra Das Sharma
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Publication number: 20170179962Abstract: Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.Type: ApplicationFiled: December 27, 2016Publication date: June 22, 2017Inventors: Wenyan Vivian Jia, Shenggao Li, Fulvio Spagna
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Publication number: 20170109315Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.Type: ApplicationFiled: December 28, 2016Publication date: April 20, 2017Applicant: Intel CorporationInventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert H. Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
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Patent number: 9626321Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration.Type: GrantFiled: October 22, 2013Date of Patent: April 18, 2017Assignee: Intel CorporationInventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
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Publication number: 20170097907Abstract: Re-initialization of a link can take place without termination of the link, where the link includes, a transmitter and a receiver are to be coupled to each lane in the number of lanes, and re-initialization of the link is to include transmission of a pre-defined sequence on each of the lanes.Type: ApplicationFiled: August 15, 2016Publication date: April 6, 2017Inventors: Venkatraman Iyer, Darren S. Jue, Robert G. Blankenship, Fulvio Spagna, Ashish Gupta
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Patent number: 9596108Abstract: Described is an apparatus which comprises: a Decision Feedback Equalizer (DFE); and a phase detector, operationally coupled to the DFE, to set a sampling phase based on a first post-cursor value of a composite pulse response being substantially equal to zero when the phase detector collects data bits having current bit and next bit such that value of the current bit is unequal to a value of the next bit.Type: GrantFiled: May 30, 2014Date of Patent: March 14, 2017Assignee: Intel CorporationInventors: Sitaraman V. Iyer, Fulvio Spagna
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Publication number: 20170019247Abstract: A redriver is provided that includes a receiver to receive a signal from a first device that includes a portion of a defined binary sequence, a drift buffer to retime the binary sequence and provide a seed to a linear feedback shift register (LFSR) from the binary sequence, the LFSR to generate an expected version of the binary sequence from the seed, and pattern checking logic to compare a sequence in subsequent signals received from the first device with the expected version of the binary sequence generated by the LFSR.Type: ApplicationFiled: September 26, 2015Publication date: January 19, 2017Inventors: Venkatraman Iyer, Fulvio Spagna, Debendra Das Sharma