Abstract: The inventive apparatus includes a first filter which receives an analog-based input signal and a feedback signal, performs equalization on the analog-based input signal and the feedback signal, and outputs an equalized signal based on the analog-based input signal and the feedback signal. The first filter may include an analog finite impulse response filter. The apparatus also includes an analog to digital converter which receives the equalized signal and outputs a digital signal converted from the equalized signal in accordance with the feedback signal. In addition, the apparatus includes a phase detector which receives the digital signal, detects a phase difference therefrom and outputs a signal corresponding to a magnitude of the phase difference. The apparatus also includes a second filter and a voltage controlled oscillator.

Abstract: A phase selector circuit for the interpolation of phase signals including a state machine for outputting data in accordance with a clock signal and a logic circuit for receiving said output data from said state machine, the logic circuit causing a clock-to-data delay for data falling longer than a clock-to-data delay for data rising.