Abstract: A nonvolatile semiconductor storage device includes a substrate; an isolation film extending in a first direction and dividing the substrate into element regions; a cell string including memory cells in the element regions; a cell unit including the cell string and a select transistor on first directional ends of the cell string; diffusion layers formed in a portion of the element region first directionally beside the select gate electrode, the diffusion layers being adjacent to one another in a second direction intersecting with the first direction; and contacts extending through an interlayer insulating film and contacting the diffusion layers. An upper surface of the isolation film located between the diffusion layers is lower than an upper surface of the substrate. A laminate of silicon oxide film and a silicon nitride film are located above the upper surface of the isolation film and below the upper surface of the substrate.

Abstract: A nonvolatile semiconductor storage device including a semiconductor substrate; a first semiconductor region being formed in the semiconductor substrate and being delineated by a first element isolation trench filled with an isolation insulating film; a second semiconductor region being formed in the semiconductor substrate and being delineated by a second element isolation trench filled with the isolation insulating film; a memory cell transistor formed in the first semiconductor region, the memory cell transistor including a first gate insulating film, a memory gate electrode including a stack of, a first conductive film, a second gate insulating film, and a second conductive film formed above the first gate insulating film; a resistor formed in the second semiconductor region, the resistor including a stack of the first gate insulating film and the first conductive film; and a first and second contact plug contacting the first conductive film of the resistor.

Abstract: According to one embodiment, a semiconductor memory device comprises: a semiconductor substrate; a first contact plug and a second contact plug on the semiconductor substrate; a first bit line being in contact with the first contact plug; and a second bit line on the second contact plug, wherein the first contact plug is in contact with a top surface of the first bit line and is electrically insulated from the second bit line, and a bottom surface of the second bit line is higher in height than the top surface of the first bit line.

Abstract: According to one embodiment, a part of a buried insulating film buried in a trench is removed; accordingly, an air gap is formed between adjacent floating gate electrodes in a word line direction, and the air gap is formed continuously along the trench in a manner of sinking below a control gate electrode.