Patents by Inventor Fumihiko Fukunaga

Fumihiko Fukunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10996569
    Abstract: An overlay measurement method using a reference image is an effective method for an overlay measurement in a product circuit. However, there is a problem that it is not possible to obtain an ideal reference image in a process of prototyping.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: May 4, 2021
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Yuji Takagi, Fumihiko Fukunaga, Yasunori Goto
  • Patent number: 10783625
    Abstract: A method for measuring overlay at a semiconductor device on which circuit patterns are formed by a plurality of exposure processes is characterized in including an image capturing step for capturing images of a plurality of areas of the semiconductor device, a reference image setting step for setting a reference image based on a plurality of the images captured in the image capturing step, a difference quantifying step for quantifying a difference between the reference image set in the reference image setting step and the plurality of images captured in the image capturing step, and an overlay calculating step for calculating the overlay based on the difference quantified in the difference quantifying step.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 22, 2020
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Minoru Harada, Ryo Nakagaki, Fumihiko Fukunaga, Yuji Takagi
  • Patent number: 10720307
    Abstract: An electron microscope device includes: a first detection means disposed at a high elevation angle for detecting electrons having relatively low energy; a second detection means disposed at a low elevation angle for detecting electrons having relatively high energy; a means for identifying, from a first image obtained from a first detector, a hole region in a semiconductor pattern within a preset region; a means for calculating for individual holes, from a second image obtained from a second detector, indexes pertaining to an inclined orientation and an inclination angle, on the basis of the distance between the outer periphery of the hole region and the hole bottom; and a means for calculating, from the results measured for the individual holes, indexes pertaining to an inclined orientation of the hole and an inclination angle of the hole as representative values for the image being measured.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: July 21, 2020
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Yuji Takagi, Fumihiko Fukunaga, Yasunori Goto
  • Patent number: 10712152
    Abstract: The purpose of the present invention is to provide an overlay error measurement device that is capable of accurately recognizing patterns and executing overlay error measurement, even when one pattern overlaps with another pattern in some areas but not in others. In order to do so, the present invention provides an overlay error measurement device provided with a calculating device for calculating overlay error. The overlay error measurement device is provided with an image designation device for designating a plurality of regions demarcated by luminance borders on an image. The calculating device recognizes, as a first pattern, a region in an image to be measured, corresponding to the plurality of regions demarcated by luminance borders, and uses the recognized first pattern to measure overlay error.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: July 14, 2020
    Assignee: Hitachi High-Tech Corporation
    Inventor: Fumihiko Fukunaga
  • Publication number: 20190362933
    Abstract: An electron microscope device includes: a first detection means disposed at a high elevation angle for detecting electrons having relatively low energy; a second detection means disposed at a low elevation angle for detecting electrons having relatively high energy; a means for identifying, from a first image obtained from a first detector, a hole region in a semiconductor pattern within a preset region; a means for calculating for individual holes, from a second image obtained from a second detector, indexes pertaining to an inclined orientation and an inclination angle, on the basis of the distance between the outer periphery of the hole region and the hole bottom; and a means for calculating, from the results measured for the individual holes, indexes pertaining to an inclined orientation of the hole and an inclination angle of the hole as representative values for the image being measured.
    Type: Application
    Filed: September 14, 2017
    Publication date: November 28, 2019
    Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Yuji TAKAGI, Fumihiko FUKUNAGA, Yasunori GOTO
  • Publication number: 20190033728
    Abstract: An overlay measurement method using a reference image is an effective method for an overlay measurement in a product circuit. However, there is a problem that it is not possible to obtain an ideal reference image in a process of prototyping.
    Type: Application
    Filed: January 27, 2016
    Publication date: January 31, 2019
    Inventors: Yuji TAKAGI, Fumihiko FUKUNAGA, Yasunori GOTO
  • Publication number: 20190017817
    Abstract: The purpose of the present invention is to provide an overlay error measurement device that is capable of accurately recognizing patterns and executing overlay error measurement, even when one pattern overlaps with another pattern in some areas but not in others. In order to do so, the present invention provides an overlay error measurement device provided with a calculating device for calculating overlay error. The overlay error measurement device is provided with an image designation device for designating a plurality of regions demarcated by luminance borders on an image. The calculating device recognizes, as a first pattern, a region in an image to be measured, corresponding to the plurality of regions demarcated by luminance borders, and uses the recognized first pattern to measure overlay error.
    Type: Application
    Filed: January 29, 2016
    Publication date: January 17, 2019
    Inventor: Fumihiko FUKUNAGA
  • Patent number: 10094658
    Abstract: To address the problem in which when measuring the overlay of patterns formed on upper and lower layers of a semiconductor pattern by comparing a reference image and measurement image obtained through imaging by an SEM, the contrast of the SEM image of the pattern of the lower layer is low relative to that of the SEM image of the pattern of the upper layer and alignment state verification is difficult even if the reference image and measurement image are superposed on the basis of measurement results, the present invention determines the amount of positional displacement of patterns of an object of overlay measurement from a reference image and measurement image obtained through imaging by an SEM, carries out differential processing on the reference image and measurement image, aligns the reference image and measurement image that have been subjected to differential processing on the basis of the positional displacement amount determined previously, expresses the gradation values of the aligned differential r
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: October 9, 2018
    Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Yuji Takagi, Fumihiko Fukunaga, Yasunori Goto
  • Publication number: 20180025482
    Abstract: A method for measuring overlay at a semiconductor device on which circuit patterns are formed by a plurality of exposure processes is characterized in including an image capturing step for capturing images of a plurality of areas of the semiconductor device, a reference image setting step for setting a reference image based on a plurality of the images captured in the image capturing step, a difference quantifying step for quantifying a difference between the reference image set in the reference image setting step and the plurality of images captured in the image capturing step, and an overlay calculating step for calculating the overlay based on the difference quantified in the difference quantifying step.
    Type: Application
    Filed: September 29, 2017
    Publication date: January 25, 2018
    Inventors: Minoru HARADA, Ryo NAKAGAKI, Fumihiko FUKUNAGA, Yuji TAKAGI
  • Patent number: 9858659
    Abstract: Provided is a pattern inspecting and measuring device that decreases the influence of noise and the like and increases the reliability of an inspection or measurement result during inspection or measurement using the position of an edge extracted from image data obtained by imaging a pattern as the object of inspection or measurement. For this purpose, in the pattern inspecting and measuring device in which inspection or measurement of an inspection or measurement object pattern is performed using the position of the edge extracted, with the use of an edge extraction parameter, from the image data obtained by imaging the inspection or measurement object pattern, the edge extraction parameter is generated using a reference pattern having a shape as an inspection or measurement reference and the image data.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: January 2, 2018
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Tsuyoshi Minakawa, Takashi Hiroi, Takeyuki Yoshida, Taku Ninomiya, Takuma Yamamoto, Hiroyuki Shindo, Fumihiko Fukunaga, Yasutaka Toyoda, Shinichi Shinoda
  • Publication number: 20170322021
    Abstract: To address the problem in which when measuring the overlay of patterns formed on upper and lower layers of a semiconductor pattern by comparing a reference image and measurement image obtained through imaging by an SEM, the contrast of the SEM image of the pattern of the lower layer is low relative to that of the SEM image of the pattern of the upper layer and alignment state verification is difficult even if the reference image and measurement image are superposed on the basis of measurement results, the present invention determines the amount of positional displacement of patterns of an object of overlay measurement from a reference image and measurement image obtained through imaging by an SEM, carries out differential processing on the reference image and measurement image, aligns the reference image and measurement image that have been subjected to differential processing on the basis of the positional displacement amount determined previously, expresses the gradation values of the aligned differential r
    Type: Application
    Filed: August 3, 2015
    Publication date: November 9, 2017
    Inventors: Yuji TAKAGI, Fumihiko FUKUNAGA, Yasunori GOTO
  • Patent number: 9799112
    Abstract: A method for measuring overlay at a semiconductor device on which circuit patterns are formed by a plurality of exposure processes is characterized in including an image capturing step for capturing images of a plurality of areas of the semiconductor device, a reference image setting step for setting a reference image based on a plurality of the images captured in the image capturing step, a difference quantifying step for quantifying a difference between the reference image set in the reference image setting step and the plurality of images captured in the image capturing step, and an overlay calculating step for calculating the overlay based on the difference quantified in the difference quantifying step.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: October 24, 2017
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Minoru Harada, Ryo Nakagaki, Fumihiko Fukunaga, Yuji Takagi
  • Patent number: 9390885
    Abstract: When a scanning electron microscope is used to measure a superposition error between upper-layer and lower-layer patterns, an SN of the lower-layer pattern may often be lower, so that when simple frame adding processing is used, the adding processing needs to be performed many times. Further, in an image obtained through such simple adding processing, contrast may not be optimal for both the upper-layer and lower-layer patterns.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: July 12, 2016
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Takuma Yamamoto, Yasunori Goto, Fumihiko Fukunaga
  • Patent number: 9342878
    Abstract: For inspection of a pattern such as a semiconductor device, it is useful to selectively detect a defect on the specific pattern in order to estimate the cause of the occurrence of the defect. An object of the invention is to provide a charged particle beam apparatus capable of setting, on the basis of the shape of the pattern on a sample, a region to be inspected. The invention is characterized in that the contour of the pattern on the sample is extracted using a template image obtained on the basis of an image of the sample, the region to be inspected is set on the basis of the contour of the pattern, a defect candidate is detected by comparing the image to be inspected with a comparative image, and the sample is inspected using a positional relationship between the region to be inspected and the defect candidate included in the region to be inspected.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: May 17, 2016
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Kohei Yamaguchi, Takehiro Hirai, Fumihiko Fukunaga
  • Publication number: 20160056014
    Abstract: When a scanning electron microscope is used to measure a superposition error between upper-layer and lower-layer patterns, an SN of the lower-layer pattern may often be lower, so that when simple frame adding processing is used, the adding processing needs to be performed many times. Further, in an image obtained through such simple adding processing, contrast may not be optimal for both the upper-layer and lower-layer patterns.
    Type: Application
    Filed: March 10, 2014
    Publication date: February 25, 2016
    Inventors: Takuma YAMAMOTO, Yasunori GOTO, Fumihiko FUKUNAGA
  • Patent number: 9165356
    Abstract: A defect inspection method for inspecting a defect on a semiconductor wafer, using plural inspection methods includes: merging hot-spot coordinates as coordinates on the semiconductor wafer, designated by a user, or coordinates where a systematic defect can occur, with detected defect coordinates on the semiconductor wafer, acquired from inspection information, after information indicating the type of coordinates are added thereto; deciding an inspection sequence of the coordinates merged with each other; and defect inspection for executing selection using the information indicating the respective types of the coordinates merged with each other, and executing an inspection by selecting an inspection method for every coordinates to be inspected.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: October 20, 2015
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Minoru Harada, Atsushi Miyamoto, Takehiro Hirai, Fumihiko Fukunaga
  • Publication number: 20150228063
    Abstract: Provided is a pattern inspecting and measuring device that decreases the influence of noise and the like and increases the reliability of an inspection or measurement result during inspection or measurement using the position of an edge extracted from image data obtained by imaging a pattern as the object of inspection or measurement. For this purpose, in the pattern inspecting and measuring device in which inspection or measurement of an inspection or measurement object pattern is performed using the position of the edge extracted, with the use of an edge extraction parameter, from the image data obtained by imaging the inspection or measurement object pattern, the edge extraction parameter is generated using a reference pattern having a shape as an inspection or measurement reference and the image data.
    Type: Application
    Filed: October 11, 2013
    Publication date: August 13, 2015
    Inventors: Tsuyoshi Minakawa, Takashi Hiroi, Takeyuki Yoshida, Taku Ninomiya, Takuma Yamamoto, Hiroyuki Shindo, Fumihiko Fukunaga, Yasutaka Toyoda, Shinichi Shinoda
  • Publication number: 20140375793
    Abstract: A method for measuring overlay at a semiconductor device on which circuit patterns are formed by a plurality of exposure processes is characterized in including an image capturing step for capturing images of a plurality of areas of the semiconductor device, a reference image setting step for setting a reference image based on a plurality of the images captured in the image capturing step, a difference quantifying step for quantifying a difference between the reference image set in the reference image setting step and the plurality of images captured in the image capturing step, and an overlay calculating step for calculating the overlay based on the difference quantified in the difference quantifying step.
    Type: Application
    Filed: February 6, 2013
    Publication date: December 25, 2014
    Inventors: Minoru Harada, Ryo Nakagaki, Fumihiko Fukunaga, Yuji Takagi
  • Publication number: 20140169657
    Abstract: A defect inspection method for inspecting a defect on a semiconductor wafer, using plural inspection methods includes: merging hot-spot coordinates as coordinates on the semiconductor wafer, designated by a user, or coordinates where a systematic defect can occur, with detected defect coordinates on the semiconductor wafer, acquired from inspection information, after information indicating the type of coordinates are added thereto; deciding an inspection sequence of the coordinates merged with each other; and defect inspection for executing selection using the information indicating the respective types of the coordinates merged with each other, and executing an inspection by selecting an inspection method for every coordinates to be inspected.
    Type: Application
    Filed: July 6, 2012
    Publication date: June 19, 2014
    Applicant: Hitachi High-Technologies Corporation
    Inventors: Minoru Harada, Atsushi Miyamoto, Takehiro Hirai, Fumihiko Fukunaga
  • Publication number: 20130265408
    Abstract: For inspection of a pattern such as a semiconductor device, it is useful to selectively detect a defect on the specific pattern in order to estimate the cause of the occurrence of the defect. An object of the invention is to provide a charged particle beam apparatus capable of setting, on the basis of the shape of the pattern on a sample, a region to be inspected. The invention is characterized in that the contour of the pattern on the sample is extracted using a template image obtained on the basis of an image of the sample, the region to be inspected is set on the basis of the contour of the pattern, a defect candidate is detected by comparing the image to be inspected with a comparative image, and the sample is inspected using a positional relationship between the region to be inspected and the defect candidate included in the region to be inspected.
    Type: Application
    Filed: October 24, 2011
    Publication date: October 10, 2013
    Inventors: Kohei Yamaguchi, Takehiro Hirai, Fumihiko Fukunaga