Patents by Inventor Fumihiko Fukunaga
Fumihiko Fukunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10996569Abstract: An overlay measurement method using a reference image is an effective method for an overlay measurement in a product circuit. However, there is a problem that it is not possible to obtain an ideal reference image in a process of prototyping.Type: GrantFiled: January 27, 2016Date of Patent: May 4, 2021Assignee: HITACHI HIGH-TECH CORPORATIONInventors: Yuji Takagi, Fumihiko Fukunaga, Yasunori Goto
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Patent number: 10783625Abstract: A method for measuring overlay at a semiconductor device on which circuit patterns are formed by a plurality of exposure processes is characterized in including an image capturing step for capturing images of a plurality of areas of the semiconductor device, a reference image setting step for setting a reference image based on a plurality of the images captured in the image capturing step, a difference quantifying step for quantifying a difference between the reference image set in the reference image setting step and the plurality of images captured in the image capturing step, and an overlay calculating step for calculating the overlay based on the difference quantified in the difference quantifying step.Type: GrantFiled: September 29, 2017Date of Patent: September 22, 2020Assignee: HITACHI HIGH-TECH CORPORATIONInventors: Minoru Harada, Ryo Nakagaki, Fumihiko Fukunaga, Yuji Takagi
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Patent number: 10720307Abstract: An electron microscope device includes: a first detection means disposed at a high elevation angle for detecting electrons having relatively low energy; a second detection means disposed at a low elevation angle for detecting electrons having relatively high energy; a means for identifying, from a first image obtained from a first detector, a hole region in a semiconductor pattern within a preset region; a means for calculating for individual holes, from a second image obtained from a second detector, indexes pertaining to an inclined orientation and an inclination angle, on the basis of the distance between the outer periphery of the hole region and the hole bottom; and a means for calculating, from the results measured for the individual holes, indexes pertaining to an inclined orientation of the hole and an inclination angle of the hole as representative values for the image being measured.Type: GrantFiled: September 14, 2017Date of Patent: July 21, 2020Assignee: Hitachi High-Technologies CorporationInventors: Yuji Takagi, Fumihiko Fukunaga, Yasunori Goto
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Patent number: 10712152Abstract: The purpose of the present invention is to provide an overlay error measurement device that is capable of accurately recognizing patterns and executing overlay error measurement, even when one pattern overlaps with another pattern in some areas but not in others. In order to do so, the present invention provides an overlay error measurement device provided with a calculating device for calculating overlay error. The overlay error measurement device is provided with an image designation device for designating a plurality of regions demarcated by luminance borders on an image. The calculating device recognizes, as a first pattern, a region in an image to be measured, corresponding to the plurality of regions demarcated by luminance borders, and uses the recognized first pattern to measure overlay error.Type: GrantFiled: January 29, 2016Date of Patent: July 14, 2020Assignee: Hitachi High-Tech CorporationInventor: Fumihiko Fukunaga
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Publication number: 20190362933Abstract: An electron microscope device includes: a first detection means disposed at a high elevation angle for detecting electrons having relatively low energy; a second detection means disposed at a low elevation angle for detecting electrons having relatively high energy; a means for identifying, from a first image obtained from a first detector, a hole region in a semiconductor pattern within a preset region; a means for calculating for individual holes, from a second image obtained from a second detector, indexes pertaining to an inclined orientation and an inclination angle, on the basis of the distance between the outer periphery of the hole region and the hole bottom; and a means for calculating, from the results measured for the individual holes, indexes pertaining to an inclined orientation of the hole and an inclination angle of the hole as representative values for the image being measured.Type: ApplicationFiled: September 14, 2017Publication date: November 28, 2019Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATIONInventors: Yuji TAKAGI, Fumihiko FUKUNAGA, Yasunori GOTO
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Publication number: 20190033728Abstract: An overlay measurement method using a reference image is an effective method for an overlay measurement in a product circuit. However, there is a problem that it is not possible to obtain an ideal reference image in a process of prototyping.Type: ApplicationFiled: January 27, 2016Publication date: January 31, 2019Inventors: Yuji TAKAGI, Fumihiko FUKUNAGA, Yasunori GOTO
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Publication number: 20190017817Abstract: The purpose of the present invention is to provide an overlay error measurement device that is capable of accurately recognizing patterns and executing overlay error measurement, even when one pattern overlaps with another pattern in some areas but not in others. In order to do so, the present invention provides an overlay error measurement device provided with a calculating device for calculating overlay error. The overlay error measurement device is provided with an image designation device for designating a plurality of regions demarcated by luminance borders on an image. The calculating device recognizes, as a first pattern, a region in an image to be measured, corresponding to the plurality of regions demarcated by luminance borders, and uses the recognized first pattern to measure overlay error.Type: ApplicationFiled: January 29, 2016Publication date: January 17, 2019Inventor: Fumihiko FUKUNAGA
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Patent number: 10094658Abstract: To address the problem in which when measuring the overlay of patterns formed on upper and lower layers of a semiconductor pattern by comparing a reference image and measurement image obtained through imaging by an SEM, the contrast of the SEM image of the pattern of the lower layer is low relative to that of the SEM image of the pattern of the upper layer and alignment state verification is difficult even if the reference image and measurement image are superposed on the basis of measurement results, the present invention determines the amount of positional displacement of patterns of an object of overlay measurement from a reference image and measurement image obtained through imaging by an SEM, carries out differential processing on the reference image and measurement image, aligns the reference image and measurement image that have been subjected to differential processing on the basis of the positional displacement amount determined previously, expresses the gradation values of the aligned differential rType: GrantFiled: August 3, 2015Date of Patent: October 9, 2018Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATIONInventors: Yuji Takagi, Fumihiko Fukunaga, Yasunori Goto
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Publication number: 20180025482Abstract: A method for measuring overlay at a semiconductor device on which circuit patterns are formed by a plurality of exposure processes is characterized in including an image capturing step for capturing images of a plurality of areas of the semiconductor device, a reference image setting step for setting a reference image based on a plurality of the images captured in the image capturing step, a difference quantifying step for quantifying a difference between the reference image set in the reference image setting step and the plurality of images captured in the image capturing step, and an overlay calculating step for calculating the overlay based on the difference quantified in the difference quantifying step.Type: ApplicationFiled: September 29, 2017Publication date: January 25, 2018Inventors: Minoru HARADA, Ryo NAKAGAKI, Fumihiko FUKUNAGA, Yuji TAKAGI
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Patent number: 9858659Abstract: Provided is a pattern inspecting and measuring device that decreases the influence of noise and the like and increases the reliability of an inspection or measurement result during inspection or measurement using the position of an edge extracted from image data obtained by imaging a pattern as the object of inspection or measurement. For this purpose, in the pattern inspecting and measuring device in which inspection or measurement of an inspection or measurement object pattern is performed using the position of the edge extracted, with the use of an edge extraction parameter, from the image data obtained by imaging the inspection or measurement object pattern, the edge extraction parameter is generated using a reference pattern having a shape as an inspection or measurement reference and the image data.Type: GrantFiled: October 11, 2013Date of Patent: January 2, 2018Assignee: Hitachi High-Technologies CorporationInventors: Tsuyoshi Minakawa, Takashi Hiroi, Takeyuki Yoshida, Taku Ninomiya, Takuma Yamamoto, Hiroyuki Shindo, Fumihiko Fukunaga, Yasutaka Toyoda, Shinichi Shinoda
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Publication number: 20170322021Abstract: To address the problem in which when measuring the overlay of patterns formed on upper and lower layers of a semiconductor pattern by comparing a reference image and measurement image obtained through imaging by an SEM, the contrast of the SEM image of the pattern of the lower layer is low relative to that of the SEM image of the pattern of the upper layer and alignment state verification is difficult even if the reference image and measurement image are superposed on the basis of measurement results, the present invention determines the amount of positional displacement of patterns of an object of overlay measurement from a reference image and measurement image obtained through imaging by an SEM, carries out differential processing on the reference image and measurement image, aligns the reference image and measurement image that have been subjected to differential processing on the basis of the positional displacement amount determined previously, expresses the gradation values of the aligned differential rType: ApplicationFiled: August 3, 2015Publication date: November 9, 2017Inventors: Yuji TAKAGI, Fumihiko FUKUNAGA, Yasunori GOTO
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Patent number: 9799112Abstract: A method for measuring overlay at a semiconductor device on which circuit patterns are formed by a plurality of exposure processes is characterized in including an image capturing step for capturing images of a plurality of areas of the semiconductor device, a reference image setting step for setting a reference image based on a plurality of the images captured in the image capturing step, a difference quantifying step for quantifying a difference between the reference image set in the reference image setting step and the plurality of images captured in the image capturing step, and an overlay calculating step for calculating the overlay based on the difference quantified in the difference quantifying step.Type: GrantFiled: February 6, 2013Date of Patent: October 24, 2017Assignee: Hitachi High-Technologies CorporationInventors: Minoru Harada, Ryo Nakagaki, Fumihiko Fukunaga, Yuji Takagi
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Patent number: 9390885Abstract: When a scanning electron microscope is used to measure a superposition error between upper-layer and lower-layer patterns, an SN of the lower-layer pattern may often be lower, so that when simple frame adding processing is used, the adding processing needs to be performed many times. Further, in an image obtained through such simple adding processing, contrast may not be optimal for both the upper-layer and lower-layer patterns.Type: GrantFiled: March 10, 2014Date of Patent: July 12, 2016Assignee: Hitachi High-Technologies CorporationInventors: Takuma Yamamoto, Yasunori Goto, Fumihiko Fukunaga
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Patent number: 9342878Abstract: For inspection of a pattern such as a semiconductor device, it is useful to selectively detect a defect on the specific pattern in order to estimate the cause of the occurrence of the defect. An object of the invention is to provide a charged particle beam apparatus capable of setting, on the basis of the shape of the pattern on a sample, a region to be inspected. The invention is characterized in that the contour of the pattern on the sample is extracted using a template image obtained on the basis of an image of the sample, the region to be inspected is set on the basis of the contour of the pattern, a defect candidate is detected by comparing the image to be inspected with a comparative image, and the sample is inspected using a positional relationship between the region to be inspected and the defect candidate included in the region to be inspected.Type: GrantFiled: October 24, 2011Date of Patent: May 17, 2016Assignee: Hitachi High-Technologies CorporationInventors: Kohei Yamaguchi, Takehiro Hirai, Fumihiko Fukunaga
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Publication number: 20160056014Abstract: When a scanning electron microscope is used to measure a superposition error between upper-layer and lower-layer patterns, an SN of the lower-layer pattern may often be lower, so that when simple frame adding processing is used, the adding processing needs to be performed many times. Further, in an image obtained through such simple adding processing, contrast may not be optimal for both the upper-layer and lower-layer patterns.Type: ApplicationFiled: March 10, 2014Publication date: February 25, 2016Inventors: Takuma YAMAMOTO, Yasunori GOTO, Fumihiko FUKUNAGA
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Patent number: 9165356Abstract: A defect inspection method for inspecting a defect on a semiconductor wafer, using plural inspection methods includes: merging hot-spot coordinates as coordinates on the semiconductor wafer, designated by a user, or coordinates where a systematic defect can occur, with detected defect coordinates on the semiconductor wafer, acquired from inspection information, after information indicating the type of coordinates are added thereto; deciding an inspection sequence of the coordinates merged with each other; and defect inspection for executing selection using the information indicating the respective types of the coordinates merged with each other, and executing an inspection by selecting an inspection method for every coordinates to be inspected.Type: GrantFiled: July 6, 2012Date of Patent: October 20, 2015Assignee: Hitachi High-Technologies CorporationInventors: Minoru Harada, Atsushi Miyamoto, Takehiro Hirai, Fumihiko Fukunaga
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Publication number: 20150228063Abstract: Provided is a pattern inspecting and measuring device that decreases the influence of noise and the like and increases the reliability of an inspection or measurement result during inspection or measurement using the position of an edge extracted from image data obtained by imaging a pattern as the object of inspection or measurement. For this purpose, in the pattern inspecting and measuring device in which inspection or measurement of an inspection or measurement object pattern is performed using the position of the edge extracted, with the use of an edge extraction parameter, from the image data obtained by imaging the inspection or measurement object pattern, the edge extraction parameter is generated using a reference pattern having a shape as an inspection or measurement reference and the image data.Type: ApplicationFiled: October 11, 2013Publication date: August 13, 2015Inventors: Tsuyoshi Minakawa, Takashi Hiroi, Takeyuki Yoshida, Taku Ninomiya, Takuma Yamamoto, Hiroyuki Shindo, Fumihiko Fukunaga, Yasutaka Toyoda, Shinichi Shinoda
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Publication number: 20140375793Abstract: A method for measuring overlay at a semiconductor device on which circuit patterns are formed by a plurality of exposure processes is characterized in including an image capturing step for capturing images of a plurality of areas of the semiconductor device, a reference image setting step for setting a reference image based on a plurality of the images captured in the image capturing step, a difference quantifying step for quantifying a difference between the reference image set in the reference image setting step and the plurality of images captured in the image capturing step, and an overlay calculating step for calculating the overlay based on the difference quantified in the difference quantifying step.Type: ApplicationFiled: February 6, 2013Publication date: December 25, 2014Inventors: Minoru Harada, Ryo Nakagaki, Fumihiko Fukunaga, Yuji Takagi
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Publication number: 20140169657Abstract: A defect inspection method for inspecting a defect on a semiconductor wafer, using plural inspection methods includes: merging hot-spot coordinates as coordinates on the semiconductor wafer, designated by a user, or coordinates where a systematic defect can occur, with detected defect coordinates on the semiconductor wafer, acquired from inspection information, after information indicating the type of coordinates are added thereto; deciding an inspection sequence of the coordinates merged with each other; and defect inspection for executing selection using the information indicating the respective types of the coordinates merged with each other, and executing an inspection by selecting an inspection method for every coordinates to be inspected.Type: ApplicationFiled: July 6, 2012Publication date: June 19, 2014Applicant: Hitachi High-Technologies CorporationInventors: Minoru Harada, Atsushi Miyamoto, Takehiro Hirai, Fumihiko Fukunaga
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Publication number: 20130265408Abstract: For inspection of a pattern such as a semiconductor device, it is useful to selectively detect a defect on the specific pattern in order to estimate the cause of the occurrence of the defect. An object of the invention is to provide a charged particle beam apparatus capable of setting, on the basis of the shape of the pattern on a sample, a region to be inspected. The invention is characterized in that the contour of the pattern on the sample is extracted using a template image obtained on the basis of an image of the sample, the region to be inspected is set on the basis of the contour of the pattern, a defect candidate is detected by comparing the image to be inspected with a comparative image, and the sample is inspected using a positional relationship between the region to be inspected and the defect candidate included in the region to be inspected.Type: ApplicationFiled: October 24, 2011Publication date: October 10, 2013Inventors: Kohei Yamaguchi, Takehiro Hirai, Fumihiko Fukunaga