Patents by Inventor Fumihiko Hayakawa
Fumihiko Hayakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10828377Abstract: An object of the present invention is to provide a method for determining whether a subject suffers from malignant lymphoma or leukemia and an agent for treating and/or preventing the disease. The present invention relates to a method for assisting in determining whether a subject suffers from, or is likely to suffer from malignant lymphoma or leukemia, comprising: a detection step of detecting at least one of a fusion mutation of a DUX4 gene, an overexpression of a DUX4 gene, and a fusion mutation of an MEF2D gene; and a determination step of determining that the subject suffers from or is likely to suffer from the disease when at least one of the fusion mutations or the overexpression is detected. Moreover, the present invention relates to a pharmaceutical composition comprising a DUX4 inhibitor as an active ingredient, for treating and/or preventing malignant lymphoma or leukemia in a subject having a fusion mutation of a DUX4 gene and an IGH or IGL gene and/or overexpression of a DUX4 gene.Type: GrantFiled: October 26, 2016Date of Patent: November 10, 2020Assignees: THE UNIVERSITY OF TOKYO, NATIONAL UNIVERSITY CORPORATION NAGOYA UNIVERSITY, AICHI PREFECTURE, NATIONAL HOSPITAL ORGANIZATIONInventors: Hiroyuki Mano, Toshihide Ueno, Takahiko Yasuda, Masahito Kawazu, Fumihiko Hayakawa, Hitoshi Kiyoi, Shinobu Tsuzuki, Tomoki Naoe
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Publication number: 20180318448Abstract: An object of the present invention is to provide a method for determining whether a subject suffers from malignant lymphoma or leukemia and an agent for treating and/or preventing the disease. The present invention relates to a method for assisting in determining whether a subject suffers from, or is likely to suffer from malignant lymphoma or leukemia, comprising: a detection step of detecting at least one of a fusion mutation of a DUX4 gene, an overexpression of a DUX4 gene, and a fusion mutation of an MEF2D gene; and a determination step of determining that the subject suffers from or is likely to suffer from the disease when at least one of the fusion mutations or the overexpression is detected. Moreover, the present invention relates to a pharmaceutical composition comprising a DUX4 inhibitor as an active ingredient, for treating and/or preventing malignant lymphoma or leukemia in a subject having a fusion mutation of a DUX4 gene and an IGH or IGL gene and/or overexpression of a DUX4 gene.Type: ApplicationFiled: October 26, 2016Publication date: November 8, 2018Inventors: Hiroyuki MANO, Toshihide UENO, Takahiko YASUDA, Masahito KAWAZU, Fumihiko HAYAKAWA, Hitoshi KIYOI, Shinobu TSUZUKI, Tomoki NAOE
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Patent number: 9672076Abstract: A system includes a CPU; an accelerator; a comparing unit that compares a first value that is based on a first processing time period elapsing until the CPU completes a first process and a second processing time period elapsing until the accelerator completes the first process, and a second value that is based on a state of use of a battery driving the CPU and the accelerator; and a selecting unit that selects any one among the CPU and the accelerator, based on a result of comparison by the comparing unit.Type: GrantFiled: September 16, 2013Date of Patent: June 6, 2017Assignee: FUJITSU LIMITEDInventors: Takahisa Suzuki, Koichiro Yamashita, Hiromasa Yamauchi, Koji Kurihara, Fumihiko Hayakawa, Naoki Odate, Tetsuo Hiraki, Toshiya Otomo
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Patent number: 9563465Abstract: A multi-task scheduling method includes assigning a first thread to a first processor; detecting a second thread that is executed after the first thread; calculating based on a load of a processor that is assigned a third thread that generates the second thread, a first time that lasts until a start of the second thread; calculating a second time that lasts until completion of execution of the first thread; and changing a first time slice of the first processor to a second time slice when the second time is greater than the first time.Type: GrantFiled: July 3, 2013Date of Patent: February 7, 2017Assignee: FUJITSU LIMITEDInventors: Hiromasa Yamauchi, Koichiro Yamashita, Takahisa Suzuki, Koji Kurihara, Fumihiko Hayakawa, Naoki Odate, Tetsuo Hiraki
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Patent number: 9483101Abstract: A multicore processor system includes multiple processors; a device; a memory that stores information of voltage and clock frequency for minimizing power consumption in connection with a number of the processors accessing to the device; and a power control unit that controls the voltage and the clock frequency of the processors on the basis of the information stored in the memory if the number of the processors accessing to the device changes.Type: GrantFiled: June 12, 2013Date of Patent: November 1, 2016Assignee: FUJITSU LIMITEDInventors: Takahisa Suzuki, Koichiro Yamashita, Hiromasa Yamauchi, Koji Kurihara, Fumihiko Hayakawa, Naoki Odate, Tetsuo Hiraki, Toshiya Otomo
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Patent number: 9471123Abstract: A power supply control method includes detecting that a result of a first function performed by a first device ceases to be displayed on a display screen; suspending power supply to the first device and supplying power to a second device, based on a detection of the result ceasing to be displayed; and causing the second device to output a response signal to a CPU in response to a control signal from the CPU.Type: GrantFiled: March 14, 2014Date of Patent: October 18, 2016Assignee: Fujitsu LimitedInventors: Tetsuo Hiraki, Hiromasa Yamauchi, Koichiro Yamashita, Fumihiko Hayakawa, Naoki Odate, Takahisa Suzuki, Koji Kurihara
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Patent number: 9241295Abstract: A communication apparatus includes a first CPU that is capable of executing a communication process at a first processing speed; a measuring unit that measures a first transmission speed when the communication process is executed with a base station; a collecting unit that collects from at least one other apparatus, a second transmission speed between the base station and the apparatus, and a second processing speed of a second CPU included in the other apparatus based on the first transmission speed; a determining unit that determines whether the communication process is to be transferred to the other apparatus, based on the second transmission speed and the second processing speed; and a transferring unit that transfers the communication process to the other apparatus based on a determination result.Type: GrantFiled: August 9, 2013Date of Patent: January 19, 2016Assignee: FUJITSU LIMITEDInventors: Toshiya Otomo, Koichiro Yamashita, Takahisa Suzuki, Hiromasa Yamauchi, Koji Kurihara, Fumihiko Hayakawa
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Patent number: 9164823Abstract: An access method is executed by a multi-core processor system. The access method includes activating a driver that corresponds to a first CPU, based on a start of execution of a first application; starting measurement of an access time period, based on access of a peripheral device; outputting, when the access time period exceeds a predetermined time period, a detection signal to reset the driver; and prohibiting, when the access time period exceeds a predetermined time period, writing into a register retaining data to be written into the peripheral device from the first CPU.Type: GrantFiled: May 14, 2013Date of Patent: October 20, 2015Assignee: FUJITSU LIMITEDInventors: Koichiro Yamashita, Hiromasa Yamauchi, Takahisa Suzuki, Koji Kurihara, Fumihiko Hayakawa
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Publication number: 20150194198Abstract: A multi-core processor system includes a memory controller that includes multiple ports and shared memory that includes physical address spaces divided among the ports. A CPU acquires from a parallel degree information table, the number of CPUs to which software that is to be executed by the multi-core processor system, is to be assigned. After this acquisition, the CPU determines the CPUs to which the software to be executed is to be assigned and sets for each CPU, physical address spaces corresponding to logical address spaces defined by the software to be executed. After this setting, the CPU notifies an address converter of the addresses and notifies the software to be executed of the start of execution.Type: ApplicationFiled: January 30, 2015Publication date: July 9, 2015Applicant: FUJITSU LIMITEDInventors: Koichiro YAMASHITA, Fumihiko Hayakawa
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Patent number: 9043507Abstract: An information processing system includes a CPU that is connected to a bus; a device that is connected to the bus; a memory that is accessed by the CPU or the device; and a power mode control circuit that sets a power consumption mode. The power mode control circuit sets the power consumption mode based on first information that indicates a cache hit or a cache miss of a cache memory in the CPU and second information that indicates an activated state or a non-activated state of the device.Type: GrantFiled: May 9, 2013Date of Patent: May 26, 2015Assignee: FUJITSU LIMITEDInventors: Koichiro Yamashita, Hiromasa Yamauchi, Takahisa Suzuki, Koji Kurihara, Fumihiko Hayakawa
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Patent number: 8990516Abstract: A multi-core processor system includes a memory controller that includes multiple ports and shared memory that includes physical address spaces divided among the ports. A CPU acquires from a parallel degree information table, the number of CPUs to which software that is to be executed by the multi-core processor system, is to be assigned. After this acquisition, the CPU determines the CPUs to which the software to be executed is to be assigned and sets for each CPU, physical address spaces corresponding to logical address spaces defined by the software to be executed. After this setting, the CPU notifies an address converter of the addresses and notifies the software to be executed of the start of execution.Type: GrantFiled: September 20, 2012Date of Patent: March 24, 2015Assignee: Fujitsu LimitedInventors: Koichiro Yamashita, Fumihiko Hayakawa
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Publication number: 20140282588Abstract: A system includes a CPU; an accelerator; a comparing unit that compares a first value that is based on a first processing time period elapsing until the CPU completes a first process and a second processing time period elapsing until the accelerator completes the first process, and a second value that is based on a state of use of a battery driving the CPU and the accelerator; and a selecting unit that selects any one among the CPU and the accelerator, based on a result of comparison by the comparing unit.Type: ApplicationFiled: September 16, 2013Publication date: September 18, 2014Applicant: FUJITSU LIMITEDInventors: Takahisa SUZUKI, Koichiro YAMASHITA, Hiromasa YAMAUCHI, Koji KURIHARA, Fumihiko HAYAKAWA, Naoki ODATE, Tetsuo HIRAKI, Toshiya OTOMO
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Publication number: 20140201546Abstract: A power supply control method includes detecting that a result of a first function performed by a first device ceases to be displayed on a display screen; suspending power supply to the first device and supplying power to a second device, based on a detection of the result ceasing to be displayed; and causing the second device to output a response signal to a CPU in response to a control signal from the CPU.Type: ApplicationFiled: March 14, 2014Publication date: July 17, 2014Applicant: FUJITSU LIMITEDInventors: Tetsuo HIRAKI, Hiromasa Yamauchi, Koichiro Yamashita, Fumihiko Hayakawa, Naoki Odate, Takahisa Suzuki, Koji Kurihara
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Publication number: 20140006666Abstract: A task scheduling method is executed by a multi-core system and includes reading from a profile memory, first information concerning operation of a first task in a single core system; calculating second information concerning operation of a second task in the multi-core system, based on the first information; and setting based on the second information, an operating environment of a core that executes the second task.Type: ApplicationFiled: September 6, 2013Publication date: January 2, 2014Applicant: FUJITSU LIMITEDInventors: Tetsuo HIRAKI, Hiromasa YAMAUCHI, Koichiro YAMASHITA, Fumihiko HAYAKAWA, Naoki ODATE, Takahisa SUZUKI, Koji KURIHARA
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Publication number: 20130331108Abstract: A communication apparatus includes a first CPU that is capable of executing a communication process at a first processing speed; a measuring unit that measures a first transmission speed when the communication process is executed with a base station; a collecting unit that collects from at least one other apparatus, a second transmission speed between the base station and the apparatus, and a second processing speed of a second CPU included in the other apparatus based on the first transmission speed; a determining unit that determines whether the communication process is to be transferred to the other apparatus, based on the second transmission speed and the second processing speed; and a transferring unit that transfers the communication process to the other apparatus based on a determination result.Type: ApplicationFiled: August 9, 2013Publication date: December 12, 2013Applicant: FUJITSU LIMITEDInventors: Toshiya OTOMO, Koichiro YAMASHITA, Takahisa SUZUKI, Hiromasa YAMAUCHI, Koji KURIHARA, Fumihiko HAYAKAWA
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Publication number: 20130318310Abstract: A processor processing method is executed by a memory controller, and includes determining based on a log of access of a shared resource by a first application, whether the first application running on a first processor operates normally; and causing a second processor to run a second application other than the first application upon the first application being determined to not be operating normally.Type: ApplicationFiled: July 24, 2013Publication date: November 28, 2013Applicant: FUJITSU LIMITEDInventors: Hiromasa Yamauchi, Koichiro Yamashita, Takahisa Suzuki, Koji Kurihara, Fumihiko Hayakawa, Toshiya Otomo
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Publication number: 20130311751Abstract: A system includes plural processors; memory that stores a program currently under execution by the processors; and a pre-loader that pre-loads into a fragment area of the memory, a target program that is to be executed and is a program other than the program currently under execution by the processors.Type: ApplicationFiled: July 24, 2013Publication date: November 21, 2013Applicant: FUJITSU LIMITEDInventors: Koji KURIHARA, Koichiro YAMASHITA, Takahisa SUZUKI, Hiromasa YAMAUCHI, Fumihiko HAYAKAWA, Naoki ODATE, Tetsuo HIRAKI, Toshiya OTOMO
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Publication number: 20130298137Abstract: A multi-task scheduling method includes assigning a first thread to a first processor; detecting a second thread that is executed after the first thread; calculating based on a load of a processor that is assigned a third thread that generates the second thread, a first time that lasts until a start of the second thread; calculating a second time that lasts until completion of execution of the first thread; and changing a first time slice of the first processor to a second time slice when the second time is greater than the first time.Type: ApplicationFiled: July 3, 2013Publication date: November 7, 2013Inventors: Hiromasa YAMAUCHI, Koichiro Yamashita, Takahisa Suzuki, Koji Kurihara, Fumihiko Hayakawa, Naoki Odate, Tetsuo Hiraki
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Publication number: 20130275790Abstract: A multicore processor system includes multiple processors; a device; a memory that stores information of voltage and clock frequency for minimizing power consumption in connection with a number of the processors accessing to the device; and a power control unit that controls the voltage and the clock frequency of the processors on the basis of the information stored in the memory if the number of the processors accessing to the device changes.Type: ApplicationFiled: June 12, 2013Publication date: October 17, 2013Inventors: Takahisa SUZUKI, Koichiro Yamashita, Hiromasa Yamauchi, Koji Kurihara, Fumihiko Hayakawa, Naoki Odate, Tetsuo Hiraki, Toshiya Otomo
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Publication number: 20130254598Abstract: An access method is executed by a multi-core processor system. The access method includes activating a driver that corresponds to a first CPU, based on a start of execution of a first application; starting measurement of an access time period, based on access of a peripheral device; outputting, when the access time period exceeds a predetermined time period, a detection signal to reset the driver; and prohibiting, when the access time period exceeds a predetermined time period, writing into a register retaining data to be written into the peripheral device from the first CPU.Type: ApplicationFiled: May 14, 2013Publication date: September 26, 2013Applicant: FUJITSU LIMITEDInventors: Koichiro YAMASHITA, Hiromasa Yamauchi, Takahisa Suzuki, Koji Kurihara, Fumihiko Hayakawa