Abstract: An information processing system includes a CPU that is connected to a bus; a device that is connected to the bus; a memory that is accessed by the CPU or the device; and a power mode control circuit that sets a power consumption mode. The power mode control circuit sets the power consumption mode based on first information that indicates a cache hit or a cache miss of a cache memory in the CPU and second information that indicates an activated state or a non-activated state of the device.

Abstract: An an address generator generates a read address. It is detected whether the generated read address is continuous to the read address previously generated. A cache unit control circuit controls the read data to be directly output to a requester of the read data without passing the read data through a cache RAM, if a cache miss occurs, and if it has been detected that the two addresses are continuous. As a result, the subsequent operations can executed even if the present operation has not been completed.

Abstract: When an input address AD is previously stored in a register 211, if a matching signal EQ1 is active, then an address queue control circuit 19A latches an offset of the input address AD into a register 241, or else, latches the input address AD into a register 212 through a selector 262. When the input address AD is previously stored in the register 241, the address queue control circuit 19A latches the input address AD into the register 212 through the selector 262. After reading the contents of the register 211, the address queue control circuit 19A shifts the offset OFS of the register 241 to the offset field of the register 211 through a selector 261, and resets a valid flag EF of the register 241.

Abstract: In an information processing device, a first address adder generates a first address representing a target for write of data or a storage location of data to be read. A second address adder generates a second address by adding 8 to the first address. First to seventh selectors appropriately select either the first address or the second address, and supply the selected address to first to seventh memory areas, respectively. An eighth memory area is supplied with the first address.

Abstract: When an input address AD is previously stored in a register 211, if a matching signal EQ1 is active, then an address queue control circuit 19A latches an offset of the input address AD into a register 241, or else, latches the input address AD into a register 212 through a selector 262. When the input address AD is previously stored in the register 241, the address queue control circuit 19A latches the input address AD into the register 212 through the selector 262. After reading the contents of the register 211, the address queue control circuit 19A shifts the offset OFS of the register 241 to the offset field of the register 211 through a selector 261, and resets a valid flag EF of the register 241.

Abstract: An an address generator generates a read address. It is detected whether the generated read address is continuous to the read address previously generated. A cache unit control circuit controls the read data to be directly output to a requester of the read data without passing the read data through a cache RAM, if a cache miss occurs, and if it has been detected that the two addresses are continuous.

Abstract: In an information processing device, a first address adder generates a first address representing a target for write of data or a storage location of data to be read. A second address adder generates a second address by adding 8 to the first address. First to seventh selectors appropriately select either the first address or the second address, and supply the selected address to first to seventh memory areas, respectively. An eighth memory area is supplied with the first address.

Abstract: In the cache memory system, tag memory RAM modules and cache memory RAM sections each capable of switching a state between an ordinary state and a low consumption power state are connected in parallel. An n-way set associative constitution in which all the tag memory RAM modules and all the cache memory RAM modules are activated in the ordinary state, is switched to/from a 1-way direct map constitution in which only a pair of the tag memory RAM module and the cache memory RAM module are activated in the ordinary state and the remaining tag memory RAM modules and cache memory RAM modules are turned into the low consumption power state based on a value of a request address, according to a power mode signal.