Patents by Inventor Fumihiko Hayashi

Fumihiko Hayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11926531
    Abstract: Flaky alumina particles including mullite in a surface layer of the flaky alumina particles. A method for producing flaky alumina particles including forming a mixture by mixing together an aluminum compound that contains elemental aluminum, a molybdenum compound that contains elemental molybdenum, and silicon or a silicon compound that contains elemental silicon, the aluminum compound being in an amount greater than or equal to 50 mass %, calculated as Al2O3, the molybdenum compound being in an amount less than or equal to 40 mass %, calculated as MoO3, the silicon or the silicon compound being in an amount of 0.5 mass % or greater and less than 10 mass %, calculated as SiO2, relative to a total mass of the flaky alumina particles taken as 100 mass %; and firing the mixture.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: March 12, 2024
    Assignee: DIC Corporation
    Inventors: Shingo Takada, Kazuo Itoya, Jian-Jun Yuan, Takayuki Kanematsu, Masamichi Hayashi, Fumihiko Maekawa, Yoshiyuki Sano
  • Patent number: 11913373
    Abstract: A variable capacity turbocharger includes a housing, a turbine impeller at least partially located in the housing, a scroll flow path located in the housing and encircling the turbine impeller, a first nozzle ring and a second nozzle ring facing each other in the housing, a nozzle flow path located between the first nozzle ring and the second nozzle ring and fluidly coupling the scroll flow path to the turbine impeller, a gap formed between the first nozzle ring and the housing, and a bearing hole located in the first nozzle ring and including an opening adjacent to the gap. The gap is located on an opposite side of the first nozzle ring to the nozzle flow path. Additionally, the gap is connected to the scroll flow path.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: February 27, 2024
    Inventors: Katsunori Hayashi, Yuji Kobayashi, Takafumi Ueda, Kazuhiro Onitsuka, Fumihiko Fukuhara
  • Patent number: 11798886
    Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor layer, a first insulating film, and a conductive film. The semiconductor layer is formed on the semiconductor substrate. A first trench reaching the semiconductor substrate is formed within the semiconductor layer. The first insulating film is formed on the inner side surface of the first trench such that a portion of the semiconductor substrate is exposed in the first trench. The conductive film is electrically connected with the semiconductor substrate and formed on the inner side surface of the first trench through the first insulating film. In plan view, a first length of the first trench in an extending direction of the first trench is greater than a second length of the first trench in a width direction perpendicular to the extending direction, and equal to or less than 30 ?m.
    Type: Grant
    Filed: October 6, 2022
    Date of Patent: October 24, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hirokazu Sayama, Fumihiko Hayashi, Junjiro Sakai
  • Publication number: 20230030778
    Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor layer, a first insulating film, and a conductive film. The semiconductor layer is formed on the semiconductor substrate. A first trench reaching the semiconductor substrate is formed within the semiconductor layer. The first insulating film is formed on the inner side surface of the first trench such that a portion of the semiconductor substrate is exposed in the first trench. The conductive film is electrically connected with the semiconductor substrate and formed on the inner side surface of the first trench through the first insulating film. In plan view, a first length of the first trench in an extending direction of the first trench is greater than a second length of the first trench in a width direction perpendicular to the extending direction, and equal to or less than 30 ?m.
    Type: Application
    Filed: October 6, 2022
    Publication date: February 2, 2023
    Inventors: Hirokazu SAYAMA, Fumihiko HAYASHI, Junjiro SAKAI
  • Patent number: 11502036
    Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor layer, a first insulating film, and a conductive film. The semiconductor layer is formed on the semiconductor substrate. A first trench reaching the semiconductor substrate is formed within the semiconductor layer. The first insulating film is formed on the inner side surface of the first trench such that a portion of the semiconductor substrate is exposed in the first trench. The conductive film is electrically connected with the semiconductor substrate and formed on the inner side surface of the first trench through the first insulating film. In plan view, a first length of the first trench in an extending direction of the first trench is greater than a second length of the first trench in a width direction perpendicular to the extending direction, and equal to or less than 30 ?m.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: November 15, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hirokazu Sayama, Fumihiko Hayashi, Junjiro Sakai
  • Publication number: 20210249353
    Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor layer, a first insulating film, and a conductive film. The semiconductor layer is formed on the semiconductor substrate. A first trench reaching the semiconductor substrate is formed within the semiconductor layer. The first insulating film is formed on the inner side surface of the first trench such that a portion of the semiconductor substrate is exposed in the first trench. The conductive film is electrically connected with the semiconductor substrate and formed on the inner side surface of the first trench through the first insulating film. In plan view, a first length of the first trench in an extending direction of the first trench is greater than a second length of the first trench in a width direction perpendicular to the extending direction, and equal to or less than 30 ?m.
    Type: Application
    Filed: February 7, 2020
    Publication date: August 12, 2021
    Inventors: Hirokazu SAYAMA, Fumihiko HAYASHI, Junjiro SAKAI
  • Patent number: 8298900
    Abstract: A method of manufacturing a nonvolatile semiconductor storage device includes sequentially forming a charge storage film, a conductive film, and a mask film on a semiconductor substrate, sequentially removing the mask film, the conductive film, and the charge storage film at a given portion to form a groove, forming a word gate electrode to fill in the groove whose inside is covered with an insulating film, after said forming the word gate electrode, removing the mask film, after said removing the mask film, forming a spacer film to cover the conductive film and the word gate electrode, etching back the spacer film to form a spacer layer on both sides of the word gate electrode through the insulating film, removing the conductive film and the charge storage film to form a control gate electrode, and forming a source drain diffusion layer.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: October 30, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Fumihiko Hayashi
  • Patent number: 8207572
    Abstract: A nonvolatile semiconductor memory device includes a first columnar protrusion and a second columnar protrusion formed to be spaced out on a surface of a semiconductor substrate, and the first and the second columnar protrusions each include a split gate nonvolatile memory cell in which a first source/drain region and a second source/drain region are formed at a surrounding part and an extremity, and in which a first layered structure, in which a charge accumulating film and a memory gate line are layered, and a second layered structure, in which a gate oxide film and a control gate line are layered, are formed on a surface of a sidewall between the surrounding part and the extremity. The first layered structure is also formed between the first and second columnar protrusions, whereby the memory gate line of the first columnar protrusion and the second columnar protrusion is connected each other.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: June 26, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroaki Mizushima, Fumihiko Hayashi
  • Publication number: 20120058618
    Abstract: A method of manufacturing a nonvolatile semiconductor storage device includes sequentially forming a charge storage film, a conductive film, and a mask film on a semiconductor substrate, sequentially removing the mask film, the conductive film, and the charge storage film at a given portion to form a groove, forming a word gate electrode to fill in the groove whose inside is covered with an insulating film, after said forming the word gate electrode, removing the mask film, after said removing the mask film, forming a spacer film to cover the conductive film and the word gate electrode, etching back the spacer film to form a spacer layer on both sides of the word gate electrode through the insulating film, removing the conductive film and the charge storage film to form a control gate electrode, and forming a source drain diffusion layer.
    Type: Application
    Filed: October 11, 2011
    Publication date: March 8, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Fumihiko Hayashi
  • Patent number: 7999306
    Abstract: A nonvolatile semiconductor storage device includes a semiconductor substrate, a charge storage layer formed above the semiconductor substrate, a control gate formed above the charge storage layer, a silicide layer formed above the control gate, a word gate formed above a side of the control gate. A top surface of the silicide layer is flat.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: August 16, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Fumihiko Hayashi
  • Patent number: 7928491
    Abstract: A semiconductor memory device has: a substrate; a memory cell transistor of a split-gate type formed on the substrate; and a reference transistor formed on the substrate and used for generating a reference current that is used in sensing data stored in the memory cell transistor. The memory cell transistor has a floating gate and a control gate, while the reference transistor is a MIS (Metal Insulator Semiconductor) transistor having a single gate electrode.
    Type: Grant
    Filed: August 16, 2006
    Date of Patent: April 19, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Masashi Nakata, Fumihiko Hayashi
  • Publication number: 20110024826
    Abstract: A nonvolatile semiconductor memory device includes a first columnar protrusion and a second columnar protrusion formed to be spaced out on a surface of a semiconductor substrate, and the first and the second columnar protrusions each include a split gate nonvolatile memory cell in which a first source/drain region and a second source/drain region are formed at a surrounding part and an extremity, and in which a first layered structure, in which a charge accumulating film and a memory gate line are layered, and a second layered structure, in which a gate oxide film and a control gate line are layered, are formed on a surface of a sidewall between the surrounding part and the extremity. The first layered structure is also formed between the first and second columnar protrusions, whereby the memory gate line of the first columnar protrusion and the second columnar protrusion is connected each other.
    Type: Application
    Filed: June 30, 2010
    Publication date: February 3, 2011
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: HIROAKI MIZUSHIMA, FUMIHIKO HAYASHI
  • Patent number: 7615557
    Abstract: This invention relates to a hydroxy-tetrahydro-naphthalene or an urea derivative formula (I) and salts thereof which are useful as active ingredients of pharmaceutical preparations, wherein A represents formula (II) or (III) wherein # represents the connection position to the molecule and Q1a, Q2a, Q3a and Q4a are defined, and E represents formula (IV) or (V) wherein # represents the connection position to the molecule and Q1b, Q2b, Q3b, Q4b, Q5b, R1b, na, ma, Xa and Ra are defined.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: November 10, 2009
    Assignee: Xention Limited
    Inventors: Axel Bouchon, Nicole Diedrichs, Achim Hermann, Klemens Lustig, Heinrich Meier, Josef Pernerstorfer, Elke Reissmuller, Jean De Vry, Muneto Mogi, Klaus Urbahns, Takeshi Yura, Hiroshi Fujishima, Masaomi Tajimi, Noriyuki Yamamoto, Yasuhiro Tsukimi, Hiroaki Yuasa, Jang Gupta, Fumihiko Hayashi
  • Publication number: 20090224306
    Abstract: A nonvolatile semiconductor storage device includes a semiconductor substrate, a charge storage layer formed above the semiconductor substrate, a control gate formed above the charge storage layer, a spacer layer formed above the control gate and a word gate formed above a side of the control gate and the spacer layer. Atop surface of the spacer layer is lower as the top surface of the spacer layer is farther from the word gate.
    Type: Application
    Filed: February 24, 2009
    Publication date: September 10, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Fumihiko Hayashi
  • Publication number: 20090224305
    Abstract: A nonvolatile semiconductor storage device includes a semiconductor substrate, a charge storage layer formed above the semiconductor substrate, a control gate formed above the charge storage layer, a silicide layer formed above the control gate, a word gate formed above a side of the control gate. A top surface of the silicide layer is flat.
    Type: Application
    Filed: February 24, 2009
    Publication date: September 10, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Fumihiko Hayashi
  • Publication number: 20080058377
    Abstract: This invention relates to bicyclic amide, carbamate or urea derivatives and salts thereof which are useful as active ingredients of pharmaceutical preparations. The bicyclic amide, carbamate or urea derivative of the present invention has vanilloid receptor (VR1) antagonistic activity, and can be used for the prophylaxis and treatment of diseases associated with VR1 activity, in particular for the treatment of urological diseases or disorders, such as detrusor overactivity (overactive bladder), urinary incontinence, neurogenic detrusor oeractivity (detrusor hyperflexia), idiopathic detrusor overactivity (detrusor instability), benign prostatic hyperplasia, and lower urinary tract symptoms; chronic pain, neuropathic pain, postoperative pain, rheumatoid arthritic pain, neuralgia, neuropathies, algesia, nerve injury, ischaemia, neurodegeneration, stroke, and inflammatory disorders such as asthma and chronic obstructive pulmonary (or airways) disease (COPD).
    Type: Application
    Filed: October 26, 2004
    Publication date: March 6, 2008
    Applicant: Bayer HealthCare AG
    Inventors: Muneto Mogi, Hiroshi Fujishima, Masaomi Tajimi, Noriyuki Yamamoto, Klaus Urbahns, Fumihiko Hayashi, Yasuhiro Tsukimi, Jang Gupta, Hiroaki Yuasa
  • Publication number: 20080045546
    Abstract: This invention relates to tetrahydro-naphthalene and urea derivatives and salts thereof which are useful as active ingredients of pharmaceutical preparations. The tetrahydro-naphthalene and urea derivatives of the present invention have vanilloid receptor (VR1) antagonistic activity, and can be used for the prophylaxis and treatment of diseases associated with VR1 activity, in particular for the treatment of urological diseases or disorders, such as detrusor overactivity (overactive bladder), urinary incontinence, neurogenic detrusor overactivity (detrusor hyperflexia), idiopathic detrusor overactivity (detrusor instability), benign prostatic hyperplasia, and lower urinary tract symptoms; chronic pain, neuropathic pain, postoperative pain, rheumatoid arthritic pain, neuralgia, neuropathies, algesia, nerve injury, ischaemia, neurodegeneration, stroke, and inflammatory disorders such as asthma and chronic obstructive pulmonary (or airways) disease (COPD).
    Type: Application
    Filed: October 2, 2004
    Publication date: February 21, 2008
    Inventors: Axel Bouchon, Nicole Diedrichs, Achim Hermann, Klemens Lustig, Heinrich Meier, Josef Pemerstorfer, Elke Reissmuller, Muneto Mogi, Takeshi Yura, Hiroshi Fujishima, Masanori Seki, Yuji Koriyama, Kayo Yasoshima, Keiko Misawa, Masaomi Tajimi, Noriyuki Yammoto, Klaus Urbahns, Fumihiko Hayashi, Yasuhiro Tsukimi, Jang Gupta
  • Publication number: 20070228444
    Abstract: A semiconductor memory device has: a substrate; a memory cell transistor of a split-gate type formed on the substrate; and a reference transistor formed on the substrate and used for generating a reference current that is used in sensing data stored in the memory cell transistor. The memory cell transistor has a floating gate and a control gate, while the reference transistor is a MIS (Metal Insulator Semiconductor) transistor having a single gate electrode.
    Type: Application
    Filed: August 16, 2006
    Publication date: October 4, 2007
    Inventors: Masashi Nakata, Fumihiko Hayashi
  • Publication number: 20070167458
    Abstract: This invention relates to a hydroxy-tetrahydro-naphthalene or an urea derivative formula (I) and salts thereof which are useful as active ingredients of pharmaceutical preparations, wherein A represents formula (II) or (III) wherein # represents the connection position to the molecule and Q1a, Q2a, Q3a and Q4a are defined, and E represents formula (IV) or (V) wherein # represents the connection position to the molecule and Q1b, Q2b, Q3b, Q4b, Q5b, R1b, na, ma, Xa and Ra are defined.
    Type: Application
    Filed: September 22, 2004
    Publication date: July 19, 2007
    Applicant: BAYER HEALTHCARE AG
    Inventors: Axel Bouchon, Nicole Diedrichs, Achim Hermann, Klemens Lustig, Heinrich Meier, Josef Pernerstorfer, Elke Reissmuller, Jean De Vry, Muneto Mogi, Klaus Urbahns, Takeshi Yura, Hiroshi Fujishima, Masaomi Tajimi, Noriyuki Yamamoto, Hiroaki Yuasa, Jang Gupta, Yasuhiro Tsukimi, Fumihiko Hayashi
  • Publication number: 20050176010
    Abstract: Reagents which regulate human transient receptor potential channel and reagents which bind to human transient receptor potential channel gene products can play a role in preventing, ameliorating, or correcting dysfunctions or diseases including, but not limited to, urinary incontinence, overactive bladder, benign prostatic hyperplasia, lower urinary tract syndromes, and CNS disorders.
    Type: Application
    Filed: April 10, 2003
    Publication date: August 11, 2005
    Applicant: Bayer HealthCare AG
    Inventors: Masahiro Shiroo, Noriyuki Yamamoto, Fumihiko Hayashi, Johannes Floeckner, Peter Reinemer, Jeffrey Encinas, Shinichi Watanabe, Masaomi Tajimi, Toshio Kokubo