Nonvolatile semiconductor storage device with charge storage layer and its manufacturing method
A nonvolatile semiconductor storage device includes a semiconductor substrate, a charge storage layer formed above the semiconductor substrate, a control gate formed above the charge storage layer, a spacer layer formed above the control gate and a word gate formed above a side of the control gate and the spacer layer. Atop surface of the spacer layer is lower as the top surface of the spacer layer is farther from the word gate.
Latest NEC Electronics Corporation Patents:
- INDUCTOR ELEMENT, INDUCTOR ELEMENT MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE WITH INDUCTOR ELEMENT MOUNTED THEREON
- Differential amplifier
- LAYOUT OF MEMORY CELLS AND INPUT/OUTPUT CIRCUITRY IN A SEMICONDUCTOR MEMORY DEVICE
- SEMICONDUCTOR DEVICE HAVING SILICON-DIFFUSED METAL WIRING LAYER AND ITS MANUFACTURING METHOD
- SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN APPARATUS, DATA PROCESSING METHOD THEREOF, AND CONTROL PROGRAM THEREOF
The present application is related to U.S. patent application Ser. No. ______, concurrently filed herewith, and which is based on Japanese Patent Application No. 2008-055598 filed on Mar. 5, 2008.
INCORPORATION BY REFERENCEThis application is based upon and claims the benefit of priority from Japanese Patent Application No. 2008-055597 which was filed on Mar. 5, 2008, the disclosure of which is incorporated herein in its entirety by reference.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to a nonvolatile semiconductor storage device and to a method of manufacturing the same, and more particularly to a charge trap type nonvolatile semiconductor storage device and to a method-of manufacturing the same.
2. Description of Related Art
As the nonvolatile semiconductor storage device, there has been known a charge trap-type nonvolatile semiconductor storage device. For example, JP-A-2004-312009 (corresponding U.S. Patent: U.S. Pat. No. 7,005,349B2) discloses a method of manufacturing a silicon-oxide-nitride-oxide-silicon (SONOS) memory device.
Then, as shown in
Subsequently, as shown in
Then, as shown in
Then, as shown in
Also, T. Saito et al., “Hot hole erase characteristics and reliability in twin MONOS device”, IEEE non-volatile semiconductor memory workshop, pp. 50-52, 2003 discloses a device of a twin-MONOS structure as a nonvolatile semiconductor memory device of a split gate-type.
With the advanced miniaturization of a memory, various characteristics required for write, erase, disturb, etc. have become increasingly severe. In order to satisfy the characteristics, the controllability of the gate length of the control gate electrode is very important.
SUMMARYHowever, in a technique (
Under the above circumstances, when a first conductive layer 130a (and a dielectric layer 111) is selectively sequentially removed with the first insulating spacer 117 as an etching mask in
Further, the magnitude of Δ1 of the taper in
The present invention seeks to solve one or more of the above problems, or to improve upon those problems at least in part.
In one exemplary embodiment, a nonvolatile semiconductor storage device according to the present invention includes a semiconductor substrate, a charge storage layer formed above the semiconductor substrate, a control gate formed above the charge storage layer, a spacer layer formed above the control gate and a word gate formed above a side of the control gate and the spacer layer. Atop surface of the spacer layer is lower as the top surface of the spacer layer is farther from the word gate.
In another exemplary embodiment, a nonvolatile semiconductor storage device according to the present invention includes a semiconductor substrate, a charge storage layer formed above the semiconductor substrate, a control gate formed above the charge storage layer, a spacer layer formed above the control gate, and a word gate formed above a side of the control gate and the spacer layer. A width of the spacer layer is narrower as the width of the spacer layer is farther from the control gate.
In yet another exemplary embodiment, a nonvolatile semiconductor storage device according to the present invention includes a semiconductor substrate, a charge storage layer formed above the semiconductor substrate, a control gate formed above the charge storage layer, a spacer layer formed above the control gate and a word gate formed above a side of the control gate and the spacer layer. A height of the spacer layer from a top surface of the control gate is lower as the top surface of the spacer layer is farther from the word gate.
Thus, in the nonvolatile semiconductor storage device according to the present invention, the spacer layer is lowered as the spacer layer is farther from the word gate or is narrower as the spacer layer is farther from the control gate. That is, the side surface of the spacer layer is not of an inversely tapered configuration in which the top surface side is projected from the bottom surface side. Accordingly, in etching with the spacer layer as a mask, the width of the control gate can be controlled by the width of the bottom surface of the spacer layer. In this case, since a variation in the width of the bottom surface of the spacer layer can be kept to a lower degree, a variation in the width of the control gate can be also kept to a lower degree. That is, a variation in the gate length being the width of the control gate can be kept low, thereby making it possible to improve the manufacture yield.
The above and other purposes, advantages and features of the present invention will become more apparent from the following description of certain exemplary embodiments taken in conjunction with the accompanying drawings in which:
The invention will now be described herein with reference to illustrative exemplary embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the knowledge of the present invention and that the invention is not limited to the exemplary embodiments illustrated for explanatory purposes.
First Exemplary EmbodimentFirst, a description will be given of the configuration of a nonvolatile semiconductor storage device according to the first exemplary embodiment of the present invention.
The memory cell 2 includes a word gate electrode 20, a word gate insulating film 15, a control gate electrode 30, an Oxide Nitride Oxide film: oxide-nitride-oxide (ONO) film 11, a spacer 17, a side wall insulating film 16, a source/drain diffusion layer 51, and silicide layers 61, 62.
The word gate electrode-20 is formed on a channel region (a surface region of the semiconductor substrate 10) through the word gate insulating film 15. The word gate electrode 20 is exemplified by polysilicon doped with impurities. A height of the word gate electrode 20 from the surface of the semiconductor substrate 10 is higher than a height of the control gate electrode 30 from the surface of the semiconductor substrate 10. As a result, when the silicide layer 62 (which will be described later) is formed on the word gate electrode 20, there is no risk that a layer that short-circuits the word gate electrode 20 and the control gate electrode 30 is formed. The word gate electrode 20 may have a top surface side larger in width than a bottom surface side as will be described later. In such a case, since an area of the silicide layer 62 can be widened, the configuration can contribute to low resistance of the silicide layer 62. The silicide layer 62 is formed on an upper portion of the word gate electrode 20. The silicide layer 62 is exemplified by a cobalt silicide.
The word gate insulating film 15 is formed on the channel region sandwiched between the source/drain diffusion layers 51 so as to cover a bottom surface and both side surfaces of the word gate electrode 20. The word gate insulating film 15 is exemplified by silicon oxide. The word gate insulating film 15 has no function of storing electric charges. That is, no electric charges are stored on the bottom surface and the side surfaces of the word gate electrode 20. No ONO film 11 (charge storage layer: described later) is located at the side surfaces of the word gate electrode 20. Instead, the word gate insulating film 15 covers the side surfaces of the word gate electrode 20, thereby making it possible to set a charge storage region to only the ONO film 11 below the control gate electrode 30. As a result, electric charges can locally exist in only the ONO film 11 facing the channel region, thereby increasing the reliability of the operation.
The control gate electrodes 30 are formed on both side surfaces of the word gate electrode 20 through the word gate insulating film 15, and on the channel region through the ONO films 11. The control gate electrodes 30 are exemplified by polysilicon doped with impurities. The top surfaces of the control gate electrodes 30 are substantially parallel to the flat surface of the semiconductor substrate 10, and are substantially flat. In the TWIN-MONOS structure shown in
Each of the ONO films 11 is a charge storage layer, and formed between the control gate electrode 30 and the channel region. The ONO film 11 may have a three-layer structure including of an oxide film 12, a nitride film 13, and an oxide film 14, which are exemplified by a silicon oxide film, a silicon nitride film, and a silicon oxide film, respectively. As described above, since the ONO film 11 is formed only in a region facing the channel region, the stored charges cannot escape to another region. As a result, it is possible to appropriately transfer electric charges by aid of the control gate electrodes 30 and the word gate electrodes 20.
Each of the spacers 17 is formed on the control gate electrode 30. The spacer layer 17 is exemplified by a silicon nitride film. A height of a top surface 17f of the spacer layer 17 from a bottom surface 17b is lower as the top surface 17f is farther from the word gate electrode 20. Also, a width of the spacer layer 17 is narrower as the spacer layer 17 is farther from the control gate electrode 30. A width of the bottom surface 17b of the spacer layer 17 coincides with a width of a top surface 30t of the control gate electrode 30, and the width of the bottom surface 17b of the spacer layer 17 corresponds to a gate length of the control gate electrode 30. Also, a side surface 17h of the spacer layer 17 at an opposite side of the word gate electrode 20 side is included in a flat surface P or located at the word gate electrode 20 side with respect to the flat surface P on which a side surface 30h of the control gate electrode 30 at an opposite side of the word gate electrode 20 side extends in a direction apart from the surface of the semiconductor substrate 10. That is, the side surface 17h has no inverse taper shown in
Each of the side wall insulating films 16 is formed so as to cover side surfaces of the control gate electrode 30, the ONO film 11, and the spacer layer 17 at an opposite side of the word gate electrode 20 side. The side wall insulating film 16 is exemplified by a unilaminate silicon oxide film, or a laminate structure including a silicon oxide film, a silicon nitride film, and a silicon oxide film. The respective gate electrodes 30 of the adjacent memory cells 2 are each surrounded by the side wall insulating film 16, and an interlayer insulating layer 19, so as to be insulated from each other.
The source/drain fusion layers 51 are formed at both sides of the channel region on the surface of the semiconductor substrate 10. Each of the source/drain diffusion layers 51 includes a low-concentration diffusion layer (LDD diffusion layer) 51a and a high-concentration diffusion layer 51b. Each of the low-concentration diffusion layers 51a is formed at a position substantially immediately below the side wall insulating film 16 so as to project from the source/drain diffusion layer 51 to the channel region. The impurities are exemplified by arsenic (As) or phosphorous (P) in the case of n-type conductivity, and exemplified by boron (B) in the case of p-type conductivity. Each of the silicide layers 61 is formed on an upper portion of the source/drain diffusion layer 51. The silicide layer 61 is exemplified by cobalt silicide. An upper portion of each silicide layer 61 is connected with a contact 71, which is further connected to a wiring 72 being an upper layer (exemplification: bit line) In the present invention, each of the spacer layers 17 becomes lower as it extends farther from the word gate electrode 20. In this case, when the flat surface P substantially perpendicular to the surface of the semiconductor substrate 10 (and a polysilicon film 20a) extends so as to include a line of intersection of the bottom surface 17b and the side surface 17h, the side surface 17h is included in the flat surface P substantially perpendicular to the side surface, or is inclined toward the word gate electrode 20 side.
In other words, the side surface 17h is not inclined toward a side apart from the word gate electrode 20 with respect to the substantially perpendicular flat surface P. That is, the side surface 17h has no inverse taper shown in
In the nonvolatile semiconductor storage device, plural memory cells 2 (a region surrounded by a broken line) are aligned in a matrix. A word gate electrode 20 extends in an X-direction, and is shared by the plural memory cells 2 aligned in the x-direction. The control gate electrodes 30 extend along both sides of the word gate electrode 20 through the word gate insulating films 15 in the X-direction, and are shared by the plural memory cells aligned in the X-direction. The word gate electrode 20 and the control gate electrodes 30 also function as wirings.
Also, on the surface of the semiconductor substrate 10 are formed plural device isolation regions 8 that electrically isolate the surface regions from each other, and extend in a Y-direction. The memory cell 2 is a region that is sandwiched between the device isolation regions 8, and includes one word gate electrode 20, the control gate electrodes at both sides of the word gate electrode 20, and regions close to the control gate electrodes 30 (source/drain diffusion layer 51). For example, the memory cell 2 is a region surrounded by a square frame (broken line) in FIG. 14. The memory cell 2 shown in
Subsequently, a description will be given of the operation of the nonvolatile semiconductor storage device according to the first exemplary embodiment with reference to
Subsequently, a description will be given of the operation of erasing information written in the memory cell 2. About 0 V is applied to the word gate electrode 20, a negative potential of about −3 V is applied to the control gate electrode 30 at the writing side, a positive potential of about 2 V is applied to the control gate electrode 30 at the non-writing side, and a positive potential of about 5 V is applied to the source/drain diffusion layer 51 at the select side. As a result, a hole electron pair occurs due to an inter-band tunnelling, and the holes or holes having occurred by colliding with those holes, are accelerated to provide hot holes which are implanted into the nitride film 14 of the ONO film 11 at the select side. As a result, negative charges that have been charged in the nitride film of the ONO film 11 are canceled to erase data.
Subsequently, a description will be given of the operation of reading information written in the memory cell 2. A positive potential of about 2 V is applied to the word gate electrode 20, a positive potential of about 2 V is applied to the control gate electrode 30 at the select side, a positive potential of about 3 V is applied to the control gate electrode 30 at the unselect side, about 0 V is applied to the source/drain diffusion layer 51 at the select side, and about 1.5V is applied to the source/drain diffusion layer 51 at the unselect side. In that state, a threshold value of the memory cell 2 is detected. When negative electric charges are stored in the ONO film 11 at the select side, the threshold value is increased to more than that in the case where the negative electric charges are not stored. Therefore, the threshold value is detected, thereby making it possible to read information read in the ONO film 11 at the select side. In the memory cell 2 shown in
Subsequently, a description will be given of a method of manufacturing the nonvolatile semiconductor storage device according to the first exemplary embodiment.
As shown in
Then, as shown in
Subsequently, as shown in
Then, as shown in
Subsequently, as shown in
Subsequently, as shown in
Then, as shown in
With the above operation, the nonvolatile semiconductor storage device (
The spacer layer 17 is formed by etch back in a process of
When the polysilicon film 30a is etched with the above spacer layer 17 as a mask, since no inverse taper exists, the polysilicon film 30a is etched by the width of the bottom surface 17b of the spacer layer 17. As a result, it is possible that a width L12 of the bottom surface 17b of the spacer layer 17 is made to coincide with a width L15 of the top surface 30t of the control gate electrode 30. That is, the width L12 of the bottom surface 17b of the spacer layer 17 can be made to correspond directly to the gate length of the control gate electrode 30. In this case, since the degree of a variation in the width L12 of the bottom surface 17b of the spacer layer 17 can be also kept low, a variation in the gate length of the control gate electrode 30 can be also kept low. That is, it is possible to improve the manufacture yield.
The manufacturing method for the nonvolatile semiconductor storage device according to the first exemplary embodiment is clearly different from the manufacturing method disclosed in JP-A-2004-312009 as shown in
As shown in
In the above state, when the spacer film 17a is formed so as to cover the word gate electrode 20 and the polysilicon film 30a in a process of
Besides, in this state, when the spacer film 17a is etched back in a process of
In this way, since the inversely tapered portion is finally eliminated or remarkably reduced, it is possible to substantially ignore the inversely tapered portion with respect to the intended spacer layer 17. Accordingly, even if the spacer layer 17 is used as an etching mask of the polysilicon film 30a, it is conceivable that etching is hardly affected by the inverse taper of the word gate electrode 20. That is, when the polysilicon film 30a is etched, etching ions reach the polysilicon film 30a while their courses are restricted by the top surface 17t and the side wall 17h of the spacer layer 17. In this situation, because the inversely tapered portion hardly exists, there is no case in which etching ions go round to that portion. Accordingly, it is possible to etch the polysilicon film 30a with a width predetermined by the top surface 17t and the sidewall 17h. Accordingly, it is possible to form the control gate electrode 30 with the width predetermined by the top surface 17t and the side wall 17h.
Also, even if the inversely tapered portion remains, and etching ions go around to that portion for etching, because a width of that portion is extremely small, its influence is similarly extremely small, and the control gate electrode 30 can be formed with a width that is rarely different from the width predetermined by the top surface 17t and the side wall 17h. Further, there is a risk that etching ions do not go around to the inversely tapered portion, or go around thereto, thereby causing the width of the control gate electrode 30 to be varied. However, as described above, because the height of the inversely tapered portion is smaller than L10A (than L10), the control gate electrode 30 can be formed with a width that is rarely different from the width predetermined by the top surface 17t and the side wall 17h regardless of the presence or degree of go-around of etching ions. Accordingly, there arises no problem on a variation in the width of the control gate electrode 30.
As described above, in the present invention, the height of the inversely tapered portion can be more surely decreased as compared with the case of JP-A-2004-312009. Further, the film thickness of the spacer layer 17a, the height (=L10) of the mask film 80, and the etch back quality are appropriately set, thereby enabling the occurrence of the inversely tapered portion to be finally removed.
Also, in the technique of JP-A-2004-312009, in order to form the control gate electrode 130, it is necessary to execute selective etching by the aid of at least three kinds of insulating films that can provide etching selectivity as the buffer layer 180, the first insulating spacer 117, and the gate dielectric layer 115 in the processes of
First, a description will be given of the configuration of the nonvolatile semiconductor storage device according to the second exemplary embodiment of the present invention.
The memory cell 2a differs from that in the first exemplary embodiment in that the control gate electrode 30 has a two-layer structure (polycide structure) including of the control gate layer 31 and the silicide layer 32. That is, the control gate electrode 30 is formed on both side surfaces of the word gate electrode 20 through the word gate insulating film 15, and on the channel region through the ONO film 111. The control gate electrode 30 includes the control gate layer 31 being a lower layer disposed on the ONO film 11, and the silicide layer 32 disposed between the control gate layer 31 and the spacer layer 17. The control gate layer 31 is exemplified by polysilicon doped with impurities, and the silicide layer 32 is exemplified by tungsten silicide. The top surface of the control gate layer 31 is substantially parallel to the flat surface of the semiconductor substrate 10, and flat. In the TWIN-MONOS structure shown in
Other configurations (including
Subsequently, a description will be given of a method of manufacturing the nonvolatile semiconductor storage device according to the second exemplary embodiment.
As shown in
Then, as shown in
Subsequently, as shown in
Then, as shown in
Subsequently, as shown in
The subsequent processes are identical with those in
Similarly, in the second exemplary embodiment, the same advantages as those in the first exemplary embodiment can be obtained. Also, in the second exemplary embodiment, the control gate electrode 30 has a two-layer structure (the polycide structure of polysilicon and silicide) including the control gate layer 31 and the silicide layer 32. For that reason, the control gate electrode 30 can be reduced in resistance, thereby enabling high-speed operation to be realized.
Third Exemplary EmbodimentFirst, a description will be given of the configuration of a nonvolatile semiconductor storage device according to a third exemplary embodiment of the present invention.
The memory cell 2b differs from that in the first exemplary embodiment in that the control gate electrode 30 is disposed at only one side of the word gate electrode 20. Other configurations (including
Subsequently, a description will be given of a method of manufacturing the nonvolatile semiconductor storage device according to the third exemplary embodiment.
Initial processes of the manufacturing method for the nonvolatile semiconductor storage device according to the third exemplary embodiment are identical with the processes in
Then, as shown in
Subsequently, as shown in
Then, as shown in
Then, as shown in
With the above operation, the nonvolatile semiconductor storage device (
Likewise, in the third exemplary embodiment, the same advantages as those in the first exemplary embodiment can be obtained. Also, in the third exemplary embodiment, since there is applied the configuration of one bit/one cell system suitable for the high speed operation in which the control gate electrode 30 is disposed at only one side of the word gate electrode 20, the high speed operation and the miniaturization of the cell size can be performed. Further, when the configuration of the third exemplary embodiment in which the control gate electrode 30 is disposed at only one side of the word gate electrode 20 is applied to the configuration of the second exemplary embodiment, still higher speed operation can be executed (
Although the invention has been described above in connection with several exemplary embodiments thereof, it will be appreciated by those skilled in the art that those embodiments are provided solely for illustrating the invention, and should not be relied upon to construe the appended claims in a limiting sense.
Further, it is noted that, notwithstanding any claim amendments made hereafter, applicant's intent is to encompass equivalents all claim elements, even if amended later during prosecution.
It is apparent to one skilled in the art that the present invention may be changed or modified without departing from the spirit and scope of the apparatus claims that are indicated in the subsequent pages as well as methods that are indicated below.
AA. A method for manufacturing a nonvolatile semiconductor storage device, comprising:
sequentially forming a charge storage layer, a conductive layer, and a mask layer above a semiconductor substrate;
sequentially removing the mask layer, the conductive layer, and the charge storage layer to form a trench;
covering an inside of the trench with an insulating layer;
forming a word gate so as to fill in the trench whose inside is covered with the insulating layer;
removing the mask layer;
forming a spacer layer so as to cover the conductive layer and the word gate;
etching the spacer layer to form a sidewall spacer above a side of the word gate via the insulating layer; and
removing the conductive layer and the charge storage layer with the sidewall spacer as a mask to form a control gate.
BB. The method according to method AA, wherein the forming of the charge storage layer, the conductive layer and the mask layer comprises forming a silicide layer on the conductive layer.
CC. The method according to method AA, wherein the charge storage layer includes a laminated layer of a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer.
DD. The method according to method AA, further comprising removing one of the spacer layers formed on both sides of the word gate before the removing the conductive layer and the charge storage layer.
EE. The method according to method AA, further comprising implanting an ion to form a diffusion layer and a second diffusion layer on the semiconductor substrate,
wherein the charge storage layer and the word gate are disposed between the first diffusion layer and the second diffusion layer.
FF. The method according to method AA, wherein a top surface of the spacer layer is lower as the top surface of the spacer layer is farther from the word gate.
GG. The method according to method AA, wherein a width of the spacer layer is narrower as the width of the spacer layer is farther from the control gate.
HH. The method according to method AA, wherein a height of the spacer layer from a top surface of the control gate is lower as the top surface of the spacer layer is farther from the word gate.
Claims
1. A nonvolatile semiconductor storage device, comprising:
- a semiconductor substrate;
- a charge storage layer formed above the semiconductor substrate;
- a control gate formed above the charge storage layer;
- a spacer layer formed above the control gate; and
- a word gate formed above a side of the control gate and the spacer layer,
- wherein a top surface of the spacer layer is lower as the top surface of the spacer layer is farther from the word gate.
2. The nonvolatile semiconductor storage device according to claim 1, wherein a top surface of the control gate is substantially flat.
3. The nonvolatile semiconductor storage device according to claim 1, wherein a height of a top surface of the word gate from the semiconductor substrate is higher than a height of a top surface of the control gate from the semiconductor substrate.
4. The nonvolatile semiconductor storage device according to claim 1, wherein the charge storage layer includes:
- a first silicon oxide layer;
- a silicon nitride layer formed above the first silicon oxide layer; and
- a second silicon oxide layer formed above the silicon nitride layer.
5. The nonvolatile semiconductor storage device according to claim 1, further comprising:
- a first diffusion layer formed on the semiconductor substrate; and
- a second diffusion layer formed on the semiconductor substrate,
- wherein the charge storage layer and the word gate are disposed between the first diffusion layer and the second diffusion layer.
6. The nonvolatile semiconductor storage device according to claim 5, further comprising:
- a first silicide layer formed on the word gate;
- a second silicide layer formed on the first diffusion layer; and
- a third silicide layer formed on the second diffusion layer.
7. The nonvolatile semiconductor storage device according to claim 1, further comprising a silicide layer formed on a top surface of the control gate.
8. The nonvolatile semiconductor storage device according to claim 6, further comprising a fourth silicide layer formed on a top surface of the control gate.
9. The nonvolatile semiconductor storage device according to claim 1, wherein the charge storage layer comprises a first charge storage layer,
- wherein the control gate comprises a first control gate,
- wherein the spacer layer comprises a first spacer layer, wherein the nonvolatile semiconductor storage device further comprises: a second charge storage layer formed above the semiconductor substrate, the first charge storage layer and the second charge storage layer being disposed symmetrically with respect to the word gate; a second control gate formed above the second charge storage layer, the first control gate and the second control gate being disposed symmetrically with respect to the word gate; and a second spacer layer formed above the second control gate, the first spacer layer and the second spacer layer being disposed symmetrically with respect to the word gate,
- wherein a top surface of the second spacer layer is lower as the top surface of the second spacer layer is farther from the word gate.
10. The nonvolatile semiconductor storage device according to claim 9, further comprising:
- a first silicide layer formed on a top surface of the first control gate; and
- a second silicide layer formed on a top surface of the second control gate.
11. The nonvolatile semiconductor storage device according to claim 9, further comprising:
- a first diffusion layer formed on the semiconductor substrate; and
- a second diffusion layer formed on the semiconductor substrate,
- wherein the first charge storage layer, the second charge storage layer and the word gate are disposed between the first diffusion layer and the second diffusion layer.
12. A nonvolatile semiconductor storage device, comprising:
- a semiconductor substrate;
- a charge storage layer formed above the semiconductor substrate;
- a control gate formed above the charge storage layer;
- a spacer layer formed above the control gate; and
- a word gate formed above a side of the control gate and the spacer layer,
- wherein a width of the spacer layer is narrower as the width of the spacer layer is farther from the control gate.
13. The nonvolatile semiconductor storage device according to claim.12, wherein a top surface of the control gate is substantially flat.
14. The nonvolatile semiconductor storage device according to claim 12, further comprising a silicide layer formed on a top surface of the control gate.
15. The nonvolatile semiconductor storage device according to claim 12, wherein the charge storage layer comprises a first charge storage layer,
- wherein the control gate comprises a first control gate,
- wherein the spacer layer comprises a first spacer layer,
- wherein the nonvolatile semiconductor storage device further comprises: a second charge storage layer formed above the semiconductor substrate, the first charge storage layer and the second charge storage layer being disposed symmetrically with respect to the word gate;
- a second control gate formed above the second charge storage layer, the first control gate and the second control gate being disposed symmetrically with respect to the word gate; and
- a second spacer layer formed above the second control gate, the first spacer layer and the second spacer layer being disposed symmetrically with respect to the word gate,
- wherein a width of the second spacer layer is narrower as the width of the second spacer layer is farther from the second control gate.
16. The nonvolatile semiconductor storage device according to claim 15, further comprising:
- a first silicide layer formed on a top surface of the first control gate; and
- a second silicide layer formed on a top surface of the second control gate.
17. A nonvolatile semiconductor storage device, comprising:
- a semiconductor substrate;
- a charge storage layer formed above the semiconductor substrate;
- a control gate formed above the charge storage layer;
- a spacer layer formed above the control gate; and
- a word gate formed above a side of the control gate and the spacer layer,
- wherein a height of the spacer layer from a top surface of the control gate is lower as the top surface of the spacer layer is farther from the word gate.
18. The nonvolatile semiconductor storage device according to claim 17, wherein a top surface of the control gate is substantially flat.
19. The nonvolatile semiconductor storage device according to claim 17, further comprising a silicide layer formed on a top surface of the control gate.
20. The nonvolatile semiconductor storage device according to claim 17, wherein the charge storage layer comprises a first charge storage layer,
- wherein the control gate comprises a first control gate,
- wherein the spacer layer comprises a first spacer layer,
- wherein the nonvolatile semiconductor storage device further comprises: a second charge storage layer formed above the semiconductor substrate, the first charge storage layer and the second charge storage layer being disposed symmetrically with respect to the word gate; a second control gate formed above the second charge storage layer, the first control gate and the second control gate being disposed symmetrically with respect to the word gate; and a second spacer layer formed above the second control gate, the first spacer layer and the second spacer layer being disposed symmetrically with respect to the word gate, wherein a height of the spacer layer from a top surface of the second control gate is lower as the top surface of the second spacer layer is farther from the word gate.
Type: Application
Filed: Feb 24, 2009
Publication Date: Sep 10, 2009
Applicant: NEC Electronics Corporation (Kawasaki)
Inventor: Fumihiko Hayashi (Kanagawa)
Application Number: 12/379,509
International Classification: H01L 29/788 (20060101);
