Patents by Inventor Fumihiko Noro
Fumihiko Noro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7951679Abstract: First, on a semiconductor region of a first conductivity type, a trapping film is formed which stores information by accumulating charges. Then, the trapping film is formed with a plurality of openings, and impurity ions of a second conductivity type are implanted into the semiconductor region from the formed openings, thereby forming a plurality of diffused layers of the second conductivity type in portions of the semiconductor region located below the openings, respectively. An insulating film is formed to cover edges of the trapping film located toward the openings, and then the semiconductor region is subjected to a thermal process in an atmosphere containing oxygen to oxidize upper portions of the diffused layers. Thereby, insulating oxide films are formed in the upper portions of the diffused layers, respectively. Subsequently, a conductive film is formed over the trapping film including the edges thereof to form an electrode.Type: GrantFiled: July 25, 2005Date of Patent: May 31, 2011Assignee: Panasonic CorporationInventors: Koji Yoshida, Keita Takahashi, Fumihiko Noro, Masatoshi Arai, Nobuyoshi Takahashi
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Patent number: 7807557Abstract: A semiconductor device includes: source/drain regions formed in a semiconductor substrate; a trapping film for storing information by accumulating charges, the trapping film being formed in a region on the semiconductor substrate which includes a region on a channel region between the source/drain regions; and gate electrodes formed on the trapping film. A silicon nitride film containing carbon is formed by low pressure CVD using an organic material so as to cover the gate electrodes and a part of the trapping film which is located between adjacent gate electrodes.Type: GrantFiled: June 5, 2007Date of Patent: October 5, 2010Assignee: Panasonic CorporationInventors: Koji Yoshida, Masataka Kusumi, Hiroaki Kuriyama, Fumihiko Noro, Nobuyoshi Takahashi
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Patent number: 7781291Abstract: A semiconductor device includes a memory section formed at a semiconductor substrate and including a first transistor having an ONO film that can store charges between the semiconductor substrate and a memory electrode and a first STI region for isolating the first transistor, and a CMOS section formed at the semiconductor substrate and including a second transistor having a CMOS electrode and a gate dielectric and a second STI region for isolating the second transistor. The height of the top surface of the first STI region is set equal to or smaller than the height of the top surface of the second STI region.Type: GrantFiled: September 1, 2009Date of Patent: August 24, 2010Assignee: Panasonic CorporationInventors: Nobuyoshi Takahashi, Satoshi Iwamoto, Fumihiko Noro, Masatoshi Arai
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Patent number: 7704803Abstract: A semiconductor device includes: a semiconductor region; a plurality of bit line diffusion layers formed in an upper portion of the semiconductor region and each extending in a row direction; a plurality of bit line insulating films formed on the bit line diffusion layers; a plurality of gate insulting films formed between the respective adjacent bit line diffusion layers on the semiconductor region; and a plurality of word lines each formed on the semiconductor region in a column direction and each intersecting with the bit line insulating films and the gate insulating films. Memory cells are formed at intersections of the gate insulating films and the word lines. A plurality of connection diffusion layers including connection parts electrically connected to the bit line diffusion layers are formed in the upper portion of the semiconductor region, and a level of upper faces of the connection parts is lower than a level of upper faces of the connection diffusion layers in the semiconductor region.Type: GrantFiled: December 17, 2008Date of Patent: April 27, 2010Assignee: Panasonic CorporationInventors: Nobuyoshi Takahashi, Fumihiko Noro, Kenji Sato
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Publication number: 20090317955Abstract: A semiconductor device includes a memory section formed at a semiconductor substrate and including a first transistor having an ONO film that can store charges between the semiconductor substrate and a memory electrode and a first STI region for isolating the first transistor, and a CMOS section formed at the semiconductor substrate and including a second transistor having a CMOS electrode and a gate dielectric and a second STI region for isolating the second transistor. The height of the top surface of the first STI region is set equal to or smaller than the height of the top surface of the second STI region.Type: ApplicationFiled: September 1, 2009Publication date: December 24, 2009Applicant: PANASONIC CORPORATIONInventors: Nobuyoshi TAKAHASHI, Satoshi Iwamoto, Fumihiko Noro, Masatoshi Arai
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Patent number: 7598589Abstract: A semiconductor device includes a memory section formed at a semiconductor substrate and including a first transistor having an ONO film that can store charges between the semiconductor substrate and a memory electrode and a first STI region for isolating the first transistor, and a CMOS section formed at the semiconductor substrate and including a second transistor having a CMOS electrode and a gate dielectric and a second STI region for isolating the second transistor. The height of the top surface of the first STI region is set equal to or smaller than the height of the top surface of the second STI region.Type: GrantFiled: June 15, 2005Date of Patent: October 6, 2009Assignee: Panasonic CorporationInventors: Nobuyoshi Takahashi, Satoshi Iwamoto, Fumihiko Noro, Masatoshi Arai
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Publication number: 20090104765Abstract: A semiconductor device includes: a semiconductor region; a plurality of bit line diffusion layers formed in an upper portion of the semiconductor region and each extending in a row direction; a plurality of bit line insulating films formed on the bit line diffusion layers; a plurality of gate insulting films formed between the respective adjacent bit line diffusion layers on the semiconductor region; and a plurality of word lines each formed on the semiconductor region in a column direction and each intersecting with the bit line insulating films and the gate insulating films. Memory cells are formed at intersections of the gate insulating films and the word lines. A plurality of connection diffusion layers including connection parts electrically connected to the bit line diffusion layers are formed in the upper portion of the semiconductor region, and a level of upper faces of the connection parts is lower than a level of upper faces of the connection diffusion layers in the semiconductor region.Type: ApplicationFiled: December 17, 2008Publication date: April 23, 2009Applicant: Matsushita Electric Industrial Co., Ltd. (PANASONIC CORPORATION)Inventors: Nobuyoshi TAKAHASHI, Fumihiko Noro, Kenji Sato
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Patent number: 7476943Abstract: A semiconductor device includes: a semiconductor region; a plurality of bit line diffusion layers formed in an upper portion of the semiconductor region and each extending in a row direction; a plurality of bit line insulating films formed on the bit line diffusion layers; a plurality of gate insulting films formed between the respective adjacent bit line diffusion layers on the semiconductor region; and a plurality of word lines each formed on the semiconductor region in a column direction and each intersecting with the bit line insulating films and the gate insulating films. Memory cells are formed at intersections of the gate insulating films and the word lines. A plurality of connection diffusion layers including connection parts electrically connected to the bit line diffusion layers are formed in the upper portion of the semiconductor region, and a level of upper faces of the connection parts is lower than a level of upper faces of the connection diffusion layers in the semiconductor region.Type: GrantFiled: April 18, 2006Date of Patent: January 13, 2009Assignee: Panasonic CorporationInventors: Nobuyoshi Takahashi, Fumihiko Noro, Kenji Sato
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Patent number: 7446381Abstract: A semiconductor memory device has a memory region which is formed on a semiconductor substrate and in which a plurality of memory cells each including a memory transistor are arranged as a matrix using a plurality of impurity diffusion layers (bit lines) and a plurality of gate electrodes (word lines) intersecting each other. The gate electrode of each of the memory transistors has an upper surface thereof formed into a protruding portion which is higher in level at the middle portion than at the edge portions. A silicide layer is formed on the upper surface of the protruding portion of the gate electrode of each of the memory transistors.Type: GrantFiled: June 14, 2005Date of Patent: November 4, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takahiko Hashidzume, Fumihiko Noro, Nobuyoshi Takahashi
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Publication number: 20080048247Abstract: A semiconductor device includes: source/drain regions formed in a semiconductor substrate; a trapping film for storing information by accumulating charges, the trapping film being formed in a region on the semiconductor substrate which includes a region on a channel region between the source/drain regions; and gate electrodes formed on the trapping film. A silicon nitride film containing carbon is formed by low pressure CVD using an organic material so as to cover the gate electrodes and a part of the trapping film which is located between adjacent gate electrodes.Type: ApplicationFiled: June 5, 2007Publication date: February 28, 2008Inventors: Koji Yoshida, Masataka Kusumi, Hiroaki Kuriyama, Fumihiko Noro, Nobuyoshi Takahashi
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Publication number: 20060237757Abstract: A semiconductor device includes: a semiconductor region; a plurality of bit line diffusion layers formed in an upper portion of the semiconductor region and each extending in a row direction; a plurality of bit line insulating films formed on the bit line diffusion layers; a plurality of gate insulting films formed between the respective adjacent bit line diffusion layers on the semiconductor region; and a plurality of word lines each formed on the semiconductor region in a column direction and each intersecting with the bit line insulating films and the gate insulating films. Memory cells are formed at intersections of the gate insulating films and the word lines. A plurality of connection diffusion layers including connection parts electrically connected to the bit line diffusion layers are formed in the upper portion of the semiconductor region, and a level of upper faces of the connection parts is lower than a level of upper faces of the connection diffusion layers in the semiconductor region.Type: ApplicationFiled: April 18, 2006Publication date: October 26, 2006Inventors: Nobuyoshi Takahashi, Fumihiko Noro, Kenji Sato
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Patent number: 7060627Abstract: A fieldless array includes a semiconductor substrate, a plurality of oxide-nitride-oxide (ONO) structures formed over the upper surface of the semiconductor substrate, and a plurality of word lines formed over the ONO structures, wherein each of the ONO structures is substantially covered by one of the word lines. The word lines (typically polysilicon) block UV irradiation during subsequent processing steps, thereby substantially preventing electrons from being trapped in the silicon nitride layer of the ONO structure. As a result, the threshold voltages of the fieldless array transistors do not severely increase as the width of the fieldless array transistors decrease.Type: GrantFiled: September 9, 2003Date of Patent: June 13, 2006Assignee: Tower Semiconductor Ltd.Inventors: Micha Gutman, Yakov Roizin, Menachem Vofsy, Efraim Aloni, Avi Ben-Gigi, Fumihiko Noro, Masatoshi Arai, Nobuyoshi Takahashi, Koji Yoshida
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Publication number: 20060086971Abstract: A semiconductor device includes a memory section formed at a semiconductor substrate and including a first transistor having an ONO film that can store charges between the semiconductor substrate and a memory electrode and a first STI region for isolating the first transistor, and a CMOS section formed at the semiconductor substrate and including a second transistor having a CMOS electrode and a gate dielectric and a second STI region for isolating the second transistor. The height of the top surface of the first STI region is set equal to or smaller than the height of the top surface of the second STI region.Type: ApplicationFiled: June 15, 2005Publication date: April 27, 2006Inventors: Nobuyoshi Takahashi, Satoshi Iwamoto, Fumihiko Noro, Masatoshi Arai
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Publication number: 20060035418Abstract: First, on a semiconductor region of a first conductivity type, a trapping film is formed which stores information by accumulating charges. Then, the trapping film is formed with a plurality of openings, and impurity ions of a second conductivity type are implanted into the semiconductor region from the formed openings, thereby forming a plurality of diffused layers of the second conductivity type in portions of the semiconductor region located below the openings, respectively. An insulating film is formed to cover edges of the trapping film located toward the openings, and then the semiconductor region is subjected to a thermal process in an atmosphere containing oxygen to oxidize upper portions of the diffused layers. Thereby, insulating oxide films are formed in the upper portions of the diffused layers, respectively. Subsequently, a conductive film is formed over the trapping film including the edges thereof to form an electrode.Type: ApplicationFiled: July 25, 2005Publication date: February 16, 2006Inventors: Koji Yoshida, Keita Takahashi, Fumihiko Noro, Masatoshi Arai, Nobuyoshi Takahashi
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Publication number: 20060022243Abstract: A semiconductor memory device has a memory region which is formed on a semiconductor substrate and in which a plurality of memory cells each including a memory transistor are arranged as a matrix using a plurality of impurity diffusion layers (bit lines) and a plurality of gate electrodes (word lines) intersecting each other. The gate electrode of each of the memory transistors has an upper surface thereof formed into a protruding portion which is higher in level at the middle portion than at the edge portions. A silicide layer is formed on the upper surface of the protruding portion of the gate electrode of each of the memory transistors.Type: ApplicationFiled: June 14, 2005Publication date: February 2, 2006Inventors: Takahiko Hashidzume, Fumihiko Noro, Nobuyoshi Takahashi
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Patent number: 6872624Abstract: A gate structure composed of a tunnel insulation film, a floating gate electrode, a capacitive insulation film and a control gate electrode is formed on a semiconductor substrate. Then, ion injection adjustment films that are in contact with the floating gate electrode at least on the side surfaces of the floating gate electrode are formed. After injecting impurity ions into the active region beside the gate structure in the semiconductor substrate while using the gate structure and the ion injection adjustment film as masks, the injected impurity ions are diffused thermally by performing heat treatment on the active region. Film thickness of the ion injection adjustment film is selected to a value to prevent the impurity ions from being injected into the tunnel insulation film and allows the impurity ions to reach lower portions of side end of the floating gate electrode in the active region as a result of diffusive scattering of impurity ions in the semiconductor substrate.Type: GrantFiled: November 13, 2001Date of Patent: March 29, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshinori Odake, Fumihiko Noro, Takahiko Hashidzume
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Patent number: 6867118Abstract: A semiconductor substrate has a memory region and a logic region isolated by an isolation insulating film. Plural memory transistors are provided in the form of a matrix in the memory region, and a logic transistor is provided in the logic region. Gate electrodes of memory transistors arranged along the word line direction out of the plural memory transistors are formed as a common gate electrode extending along the word line direction, and impurity diffusion layers working as source/drain regions of memory transistors arranged along the bit line direction are formed as a common impurity diffusion layer extending along the bit line direction. An inter-gate insulating film having its top face at a lower level than the gate electrodes is formed on the semiconductor substrate between the gate electrodes of the plural memory transistors. A sidewall insulating film is formed on the side face of a gate electrode of the logic transistor.Type: GrantFiled: May 29, 2003Date of Patent: March 15, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Fumihiko Noro
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Publication number: 20050051837Abstract: Using a rapid thermal oxidation device, the top and side surfaces of a floating gate electrode are oxidized by In Situ Steam Generation (ISSG), wherein oxygen to which about 0.5 to 33% hydrogen has been added is introduced directly into a chamber with a temperature of approximately 900 to 1100° C. and a pressure of approximately 1,000 to 2,000 Pa, in order to generate water vapor from the introduced hydrogen and oxygen on a heated semiconductor substrate. Thus, an insulating film made of silicon oxide is formed on the surface of the floating gate electrode.Type: ApplicationFiled: October 18, 2004Publication date: March 10, 2005Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Hiromasa Fujimoto, Fumihiko Noro, Masataka Kusumi
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Publication number: 20050054161Abstract: A fieldless array includes a semiconductor substrate, a plurality of oxide-nitride-oxide (ONO) structures formed over the upper surface of the semiconductor substrate, and a plurality of word lines formed over the ONO structures, wherein each of the ONO structures is substantially covered by one of the word lines. The word lines (typically polysilicon) block UV irradiation during subsequent processing steps, thereby substantially preventing electrons from being trapped in the silicon nitride layer of the ONO structure. As a result, the threshold voltages of the fieldless array transistors do not severely increase as the width of the fieldless array transistors decrease.Type: ApplicationFiled: September 9, 2003Publication date: March 10, 2005Inventors: Micha Gutman, Yakov Roizin, Menachem Vofsy, Efraim Aloni, Avi Ben-Gigi, Fumihiko Noro, Masatoshi Arai, Nobuyoshi Takahashi, Koji Yoshida
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Patent number: 6830973Abstract: Using a rapid thermal oxidation device, the top and side surfaces of a floating gate electrode are oxidized by In Situ Steam Generation (ISSG), wherein oxygen to which about 0.5 to 33% hydrogen has been added is introduced directly into a chamber with a temperature of approximately 900 to 1100° C. and a pressure of approximately 1,000 to 2,000 Pa, in order to generate water vapor from the introduced hydrogen and oxygen on a heated semiconductor substrate. Thus, an insulating film made of silicon oxide is formed on the surface of the floating gate electrode.Type: GrantFiled: September 11, 2002Date of Patent: December 14, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiromasa Fujimoto, Fumihiko Noro, Masataka Kusumi