Patents by Inventor Fumihiko Noro
Fumihiko Noro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6828621Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.Type: GrantFiled: October 7, 2003Date of Patent: December 7, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka, Seiki Ogura
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Patent number: 6791139Abstract: A semiconductor memory has first and second active regions that have been defined in a semiconductor substrate and electrically isolated from each other. Over the first active region, a control gate electrode has been formed with a control gate insulating film interposed therebetween. A floating gate electrode has been formed adjacent to a side face of the control gate electrode with a capacitive insulating film interposed therebetween. A tunnel insulating film is interposed between the first active region and the floating gate electrode. A gate electrode has been formed over the second active region with a gate insulating film interposed therebetween. Source/drain regions have been defined in respective parts of the second active region beside the gate electrode. Only the source/drain regions and the gate electrode have their upper surface covered with a metal silicide film.Type: GrantFiled: February 14, 2003Date of Patent: September 14, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Fumihiko Noro, Seiki Ogura
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Patent number: 6784040Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.Type: GrantFiled: March 7, 2003Date of Patent: August 31, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka, Seiki Ogura
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Patent number: 6734067Abstract: The invention provides a floating gate semiconductor storage device equipped with an erase gate electrode that includes first and second diffusion layers, an isolation insulating film, a gate insulating film, a floating gate electrode, a control gate electrode, a capacitor dielectric film, an erase gate electrode and a tunneling insulating film. In manufacturing the semiconductor storage device, after forming the first and second diffusion layers in a semiconductor substrate, an insulating film for isolation is deposited on the semiconductor substrate. The insulating film for isolation is simultaneously or individually patterned into an isolation insulating film and first and second lower contact holes respectively reaching the first and second diffusion layers. The semiconductor device includes first and second contact members filled in the first and second lower contact holes to be in contact with the first and second diffusion layers.Type: GrantFiled: June 12, 2002Date of Patent: May 11, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Fumihiko Noro
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Publication number: 20040071024Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.Type: ApplicationFiled: October 7, 2003Publication date: April 15, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka, Seiki Ogura
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Patent number: 6686622Abstract: A semiconductor memory device includes a control gate electrode formed on a first main surface of a semiconductor substrate through a first insulating film, and a floating gate electrode covering a stepped region which connects the first main surface of the semiconductor substrate and a second main surface positioned at a lower level than the first main surface through a second insulating film and having a side surface capacitively coupled with one side surface of the control gate electrode through a third insulating film. The stepped region has a first stepped portion connected with the first main surface and a second stepped portion connecting the first stepped portion and the second main surface.Type: GrantFiled: February 20, 2002Date of Patent: February 3, 2004Assignees: Matsushita Electric Industrial Co., Ltd., Halo LSI Design and Device Technologies Inc.Inventors: Fumihiko Noro, Seiki Ogura
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Publication number: 20030222293Abstract: A semiconductor substrate has a memory region and a logic region isolated by an isolation insulating film. Plural memory transistors are provided in the form of a matrix in the memory region, and a logic transistor is provided in the logic region. Gate electrodes of memory transistors arranged along the word line direction out of the plural memory transistors are formed as a common gate electrode extending along the word line direction, and impurity diffusion layers working as source/drain regions of memory transistors arranged along the bit line direction are formed as a common impurity diffusion layer extending along the bit line direction. An inter-gate insulating film having its top face at a lower level than the gate electrodes is formed on the semiconductor substrate between the gate electrodes of the plural memory transistors. A sidewall insulating film is formed on the side face of a gate electrode of the logic transistor.Type: ApplicationFiled: May 29, 2003Publication date: December 4, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventor: Fumihiko Noro
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Patent number: 6642572Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.Type: GrantFiled: March 7, 2003Date of Patent: November 4, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka, Seiki Ogura
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Publication number: 20030173616Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.Type: ApplicationFiled: March 7, 2003Publication date: September 18, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka, Seiki Ogura
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Publication number: 20030141540Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.Type: ApplicationFiled: March 7, 2003Publication date: July 31, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka, Seiki Ogura
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Publication number: 20030116789Abstract: A semiconductor memory has first and second active regions that have been defined in a semiconductor substrate and electrically isolated from each other. Over the first active region, a control gate electrode has been formed with a control gate insulating film interposed therebetween. A floating gate electrode has been formed adjacent to a side face of the control gate electrode with a capacitive insulating film interposed therebetween. A tunnel insulating film is interposed between the first active region and the floating gate electrode. A gate electrode has been formed over the second active region with a gate insulating film interposed therebetween. Source/drain regions have been defined in respective parts of the second active region beside the gate electrode. Only the source/drain regions and the gate electrode have their upper surface covered with a metal silicide film.Type: ApplicationFiled: February 14, 2003Publication date: June 26, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Fumihiko Noro, Seiki Ogura
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Patent number: 6558997Abstract: A semiconductor memory has first and second active regions that have been defined in a semiconductor substrate and electrically isolated from each other. Over the first active region, a control gate electrode has been formed with a control gate insulating film interposed therebetween. A floating gate electrode has been formed adjacent to a side face of the control gate electrode with a capacitive insulating film interposed therebetween. A tunnel insulating film is interposed between the first active region and the floating gate electrode. A gate electrode has been formed over the second active region with a gate insulating film interposed therebetween. Source/drain regions have been defined in respective parts of the second active region beside the gate electrode. Only the source/drain regions and the gate electrode have their upper surface covered with a metal silicide film.Type: GrantFiled: August 31, 2001Date of Patent: May 6, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Fumihiko Noro, Seiki Ogura
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Patent number: 6545312Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.Type: GrantFiled: July 3, 2001Date of Patent: April 8, 2003Assignees: Matsushita Electric Industrial Co., Ltd., Halo LSI Design and Device Technologies Inc.Inventors: Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka, Seiki Ogura
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Publication number: 20030047775Abstract: Using a rapid thermal oxidation device, the top and side surfaces of a floating gate electrode are oxidized by In Situ Steam Generation (ISSG), wherein oxygen to which about 0.5 to 33% hydrogen has been added is introduced directly into a chamber with a temperature of approximately 900 to 1100° C. and a pressure of approximately 1,000 to 2,000 Pa, in order to generate water vapor from the introduced hydrogen and oxygen on a heated semiconductor substrate. Thus, an insulating film made of silicon oxide is formed on the surface of the floating gate electrode.Type: ApplicationFiled: September 11, 2002Publication date: March 13, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Hiromasa Fujimoto, Fumihiko Noro, Masataka Kusumi
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Publication number: 20030042533Abstract: A semiconductor memory device includes a control gate electrode formed on a first main surface of a semiconductor substrate through a first insulating film, and a floating gate electrode covering a stepped region which connects the first main surface of the semiconductor substrate and a second main surface positioned at a lower level than the first main surface through a second insulating film and having a side surface capacitively coupled with one side surface of the control gate electrode through a third insulating film. The stepped region has a first stepped portion connected with the first main surface and a second stepped portion connecting the first stepped portion and the second main surface.Type: ApplicationFiled: February 20, 2002Publication date: March 6, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Fumihiko Noro, Seiki Ogura
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Publication number: 20020155664Abstract: The invention provides a floating gate semiconductor storage device equipped with an erase gate electrode that includes first and second diffusion layers, an isolation insulating film, a gate insulating film, a floating gate electrode, a control gate electrode, a capacitor dielectric film, an erase gate electrode and a tunneling insulating film. In manufacturing the semiconductor storage device, after forming the first and second diffusion layers in a semiconductor substrate, an insulating film for isolation is deposited on the semiconductor substrate. The insulating film for isolation is simultaneously or individually patterned into an isolation insulating film and first and second lower contact holes respectively reaching the first and second diffusion layers. The semiconductor device includes first and second contact members filled in the first and second lower contact holes to be in contact with the first and second diffusion layers.Type: ApplicationFiled: June 12, 2002Publication date: October 24, 2002Applicant: MATSUSHITA ELECTRONICS CORPORATIONInventor: Fumihiko Noro
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Publication number: 20020106859Abstract: A gate structure composed of a tunnel insulation film, a floating gate electrode, a capacitive insulation film and a control gate electrode is formed on a semiconductor substrate. Then, ion injection adjustment films that are in contact with the floating gate electrode at least on the side surfaces of the floating gate electrode are formed. After injecting impurity ions into the active region beside the gate structure in the semiconductor substrate while using the gate structure and the ion injection adjustment film as masks, the injected impurity ions are diffused thermally by performing heat treatment on the active region. Film thickness of the ion injection adjustment film is selected to a value to prevent the impurity ions from being injected into the tunnel insulation film and allows the impurity ions to reach lower portions of side end of the floating gate electrode in the active region as a result of diffusive scattering of impurity ions in the semiconductor substrate.Type: ApplicationFiled: November 13, 2001Publication date: August 8, 2002Inventors: Yoshinori Odake, Fumihiko Noro, Takahiko Hashidzume
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Publication number: 20020039822Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.Type: ApplicationFiled: July 3, 2001Publication date: April 4, 2002Inventors: Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka, Seiki Ogura
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Publication number: 20020031018Abstract: A semiconductor memory has first and second active regions that have been defined in a semiconductor substrate and electrically isolated from each other. Over the first active region, a control gate electrode has been formed with a control gate insulating film interposed therebetween. A floating gate electrode has been formed adjacent to a side face of the control gate electrode with a capacitive insulating film interposed therebetween. A tunnel insulating film is interposed between the first active region and the floating gate electrode. A gate electrode has been formed over the second active region with a gate insulating film interposed therebetween. Source/drain regions have been defined in respective parts of the second active region beside the gate electrode. Only the source/drain regions and the gate electrode have their upper surface covered with a metal silicide film.Type: ApplicationFiled: August 31, 2001Publication date: March 14, 2002Inventors: Fumihiko Noro, Seiki Ogura
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Patent number: 6320217Abstract: Conventionally, an insulating film for element isolation has had a uniformly large thickness either in a memory cell area and in a peripheral circuit area so that the total film thickness of the memory cell area having a floating gate electrode, a control gate electrode, and an erase gate electrode is extremely increased, resulting in a large height difference between the memory cell area and the peripheral circuit area. The insulating film for element isolation in the peripheral circuit area should be thick, while the insulating films for element isolation in the memory cell area need not be as thick as the insulating film for element isolation in the peripheral circuit area in terms of operation.Type: GrantFiled: February 24, 1999Date of Patent: November 20, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masanori Tagami, Fumihiko Noro