Abstract: The purpose of the present invention is to provide a method for determining the fraction unbound (fu) of compounds including compounds having a high protein binding ratio with accuracy and in a short time.

Abstract: A semiconductor integrated circuit according to an embodiment includes an A/D converter, first and second equalizer circuits, and first and second controllers. The first equalizer circuit includes a first tap. The first and second equalizer circuits receive a signal based on a digital signal, and output first and second signals, respectively. The first controller adjusts a phase of a clock signal based on the first signal. The second controller an operation of adjusting a control parameter including a tap coefficient. In the operation, the second controller adjusts a tap coefficient of each of taps of the second equalizer circuit, and adjusts a tap coefficient of the first tap based on an adjustment result of each tap coefficient of the second equalizer circuit.

Abstract: According to one embodiment, a semiconductor integrated circuit includes: a converter configured to convert an analog signal into a digital signal based on a clock signal; a comparator configured to determine first data having data of a first number of bits per symbol and second data having data of a second number of bits, less than the first number, per symbol based on the digital signal; a recovery circuit configured to recover the clock signal; and a control circuit configured to input the digital signal and the first data to the recovery circuit in a case where a condition is not satisfied, and to input the digital signal and the second data to the recovery circuit in a case where the condition is satisfied.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a first converter, a second converter, and an adjustment circuit. The first converter is configured to sample an analog signal and convert the sampled analog signal to a first digital value based on a first clock signal. The second converter is configured to sample the analog signal and convert the sampled analog signal to a second digital value based on a second clock signal shifted a first phase from the first clock signal. The adjustment circuit is configured to adjust at least one of a gain of each of the first digital value and the second digital value and a phase of each of the first clock signal and the second clock signal based on the first digital value and the second digital value.

Abstract: According to one embodiment, a semiconductor integrated circuit includes: a converter configured to convert an analog signal into a digital signal based on a clock signal; a comparator configured to determine first data having data of a first number of bits per symbol and second data having data of a second number of bits, less than the first number, per symbol based on the digital signal; a recovery circuit configured to recover the clock signal; and a control circuit configured to input the digital signal and the first data to the recovery circuit in a case where a condition is not satisfied, and to input the digital signal and the second data to the recovery circuit in a case where the condition is satisfied.

Abstract: An arithmetic device includes a first memory cell, a first bit line, a first transistor, a second memory cell, a second bit line, a second transistor, a third bit line, a first switching circuit, a second switching circuit and a controller. The controller sets a conduction state between the first memory cell and the first bit line by the first transistor, and sets a conduction state between the second memory cell and the second bit line by the second transistor. The controller sets the first switching circuit and the second switching circuit in a coupled state and sets the conduction state between the first bit line and the third bit line and between the second bit line and the third bit line to transition voltages of the first, second and third bit lines to a first voltage.

Abstract: According to one embodiment, an apparatus includes a processor and a memory. The processor performs a learning process of a neural network including a batch normalization layer. The processor sets up the neural network. The processor updates, in the learning process, a weight parameter and a normalization parameter, used in the normalization of the batch normalization layer, alternately or at different timings.

Abstract: A semiconductor integrated circuit includes a converter converting an analog signal into a digital signal based on a clock signal; a comparator determining values of data based on the digital signal; a recovery circuit recovering the clock signal based on the digital signal and the data; and a control circuit. The recovery circuit includes a phase detector calculating a sum of a first value and offset, the first value being a value based on the digital signal and the data and relating to a phase of the clock signal; and a loop filter calculating a correction amount of the phase of the clock signal based on the sum. The control circuit is configured to gradually change the offset from a second value to zero after the second value is added as the offset.

Abstract: According to one embodiment, an information processing method includes performing, in an intermediate layer of a deep neural network, a forward propagation using a first parameter and based on a first input value represented by a first bit number; performing quantization to produce a second input value represented by a second bit number smaller than the first bit number, and storing the produced second input value in the memory; calculating a second parameter based on a result of an operation using the second input value stored in the memory and a value obtained by the forward propagation, the second parameter being an update of the first parameter and for use in the learning process; and determining a condition for the quantization based on a gradient difference obtained in said calculating the second parameter.

Abstract: A semiconductor integrated circuit according to an embodiment includes an A/D converter, first and second equalizer circuits, and first and second controllers. The first equalizer circuit includes a first tap. The first and second equalizer circuits receive a signal based on a digital signal, and output first and second signals, respectively. The first controller adjusts a phase of a clock signal based on the first signal. The second controller an operation of adjusting a control parameter including a tap coefficient. In the operation, the second controller adjusts a tap coefficient of each of taps of the second equalizer circuit, and adjusts a tap coefficient of the first tap based on an adjustment result of each tap coefficient of the second equalizer circuit.

Abstract: According to one embodiment, an arithmetic device includes a first memory cell, a first bit line, a first transistor, a second memory cell, a second bit line, a second transistor, a third bit line, a first switching circuit, a second switching circuit and a controller. The controller sets a conduction state between the first memory cell and the first bit line by the first transistor, and sets a conduction state between the second memory cell and the second bit line by the second transistor. The controller sets the first switching circuit and the second switching circuit in a coupled state and sets the conduction state between the first bit line and the third bit line and between the second bit line and the third bit line to transition voltages of the first, second and third bit lines to a first voltage.

Abstract: According to one embodiment, a training device includes a first memory, a second memory, and a processing circuit. The first memory is a memory accessible at a higher speed than the second memory. The training device executes a training process of a machine learning model using a stochastic gradient descent method. The processing circuit stores a first output produced by the process of a first layer in the second memory, and stores a second output produced by the process of a second layer, in a forward process of the training process. The processing circuit updates a parameter of the second layer based on the second output stored in the first memory, reads the first output stored in the second memory, and updates a parameter of the first layer based on the read first output, in a backward process of the training process.

Abstract: According to one embodiment, an information processing method includes performing, in an intermediate layer of a deep neural network, a forward propagation using a first parameter and based on a first input value represented by a first bit number; performing quantization to produce a second input value represented by a second bit number smaller than the first bit number, and storing the produced second input value in the memory; calculating a second parameter based on a result of an operation using the second input value stored in the memory and a value obtained by the forward propagation, the second parameter being an update of the first parameter and for use in the learning process; and determining a condition for the quantization based on a gradient difference obtained in said calculating the second parameter.

Abstract: According to one embodiment, an information processing method for a neural network model optimized by a training by using a processor and a memory includes: outputting a first information processing result by the neural network model using first input data; and outputting a second information processing result by the neural network model using second input data obtained by applying a perturbation to the first input data. The method further includes determining a reliability of the neural network model using the first input data based on a comparison result between the first information processing result and the second information processing result.

Abstract: According to one embodiment, a method of a learning processing of a deep layer neural network having an intermediate layer including a convolution layer, in an information processing using a processor and a memory used for an operation of the processor, includes: acquiring a second value represented by the second number of bits obtained by reducing the first number of bits representing a first value being an input value in units of channel in the intermediate layer of the deep layer neural network; and storing the acquired second value of the second number of bits into the memory. The method further includes performing a back propagation using the second value stored in the memory instead of the first value.

Abstract: According to one embodiment, an apparatus includes a processor and a memory. The processor performs a learning process of a neural network including a batch normalization layer. The processor sets up the neural network. The processor updates, in the learning process, a weight parameter and a normalization parameter, used in the normalization of the batch normalization layer, alternately or at different timings.

Abstract: According to one embodiment, a transmitter includes a 1st circuit configured to execute a 1st band limitation by waveform shaping in a time region with respect to 1st data relating to a 1st channel to generate a 1st signal; a 2nd circuit configured to execute a 2nd band limitation by the waveform shaping in the time region with respect to 2nd data relating to a 2nd channel to generate a 2nd signal; a 3rd circuit configured to generate a 3rd signal based on the 1st signal and a 1st frequency relating to the 1st channel; a 4th circuit configured to generate a 4th signal based on the 2nd signal and a 2nd frequency relating to the 2nd channel; and a 5th circuit configured to generate a 5th signal by multiplexing the 3rd signal and the 4th signal.

Abstract: According to one embodiment, an information processing apparatus for convolution operations in layers of a convolutional neural network, includes a memory and a product-sum operating circuitry. The memory is configured to store items of information indicative of an input, a weight to the input, and a bit width determined for each filter of the weight. The product-sum operating circuitry is configured to perform a product-sum operation based on the items of information indicative of the input, the weight, and the bit width, stored in the memory.

Abstract: A memcapacitor according to an embodiment includes a first electrode, a first dielectric layer provided on the first electrode, a plurality of variable resistance portions provided separately from each other on the first dielectric layer, a second dielectric layer provided on the first dielectric layer and between the variable resistance portions, and a second electrode provided on the variable resistance portions and the second dielectric layer. Each of the variable resistance portions is formed of a material that allows diffusion of metal atoms constituting the second electrode to inside of the variable resistance portion, and the second dielectric layer is formed of a material that prevents diffusion of the metal atoms constituting the second electrode to inside of the second dielectric layer.

Abstract: An arithmetic device includes: an arithmetic circuit that includes arithmetic elements connected in series, and sequentially performs multiple repetitions of arithmetic processing, wherein each of the arithmetic elements receives a first time signal and a second time signal, and generates a third time signal and a fourth time signal obtained by delaying the first and second time signals by a time corresponding to a weight coefficient and input data; a converter that converts a difference between the third and fourth time signals output from the arithmetic circuit into an analog signal or a digital signal for every multiple repetition of arithmetic processing; an integrator that integrates analog signals or digital signals converted by the converter; and a comparator that compares the integration result by the integrator with a reference value.