Patents by Inventor Fumihiko Tachibana

Fumihiko Tachibana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200302287
    Abstract: According to one embodiment, an information processing method for a neural network model optimized by a training by using a processor and a memory includes: outputting a first information processing result by the neural network model using first input data; and outputting a second information processing result by the neural network model using second input data obtained by applying a perturbation to the first input data. The method further includes determining a reliability of the neural network model using the first input data based on a comparison result between the first information processing result and the second information processing result.
    Type: Application
    Filed: September 10, 2019
    Publication date: September 24, 2020
    Applicant: Toshiba Memory Corporation
    Inventor: Fumihiko TACHIBANA
  • Publication number: 20200293895
    Abstract: According to one embodiment, a method of a learning processing of a deep layer neural network having an intermediate layer including a convolution layer, in an information processing using a processor and a memory used for an operation of the processor, includes: acquiring a second value represented by the second number of bits obtained by reducing the first number of bits representing a first value being an input value in units of channel in the intermediate layer of the deep layer neural network; and storing the acquired second value of the second number of bits into the memory. The method further includes performing a back propagation using the second value stored in the memory instead of the first value.
    Type: Application
    Filed: September 10, 2019
    Publication date: September 17, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Fumihiko TACHIBANA, Daisuke MIYASHITA
  • Publication number: 20200257983
    Abstract: According to one embodiment, an apparatus includes a processor and a memory. The processor performs a learning process of a neural network including a batch normalization layer. The processor sets up the neural network. The processor updates, in the learning process, a weight parameter and a normalization parameter, used in the normalization of the batch normalization layer, alternately or at different timings.
    Type: Application
    Filed: September 9, 2019
    Publication date: August 13, 2020
    Applicant: Toshiba Memory Corporation
    Inventor: Fumihiko TACHIBANA
  • Patent number: 10553284
    Abstract: According to one embodiment, a transmitter includes a 1st circuit configured to execute a 1st band limitation by waveform shaping in a time region with respect to 1st data relating to a 1st channel to generate a 1st signal; a 2nd circuit configured to execute a 2nd band limitation by the waveform shaping in the time region with respect to 2nd data relating to a 2nd channel to generate a 2nd signal; a 3rd circuit configured to generate a 3rd signal based on the 1st signal and a 1st frequency relating to the 1st channel; a 4th circuit configured to generate a 4th signal based on the 2nd signal and a 2nd frequency relating to the 2nd channel; and a 5th circuit configured to generate a 5th signal by multiplexing the 3rd signal and the 4th signal.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: February 4, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yuta Tsubouchi, Jun Deguchi, Daisuke Miyashita, Makoto Morimoto, Junji Wadatsumi, Fumihiko Tachibana, Yuji Satoh, Takashi Toi
  • Publication number: 20200026998
    Abstract: According to one embodiment, an information processing apparatus for convolution operations in layers of a convolutional neural network, includes a memory and a product-sum operating circuitry. The memory is configured to store items of information indicative of an input, a weight to the input, and a bit width determined for each filter of the weight. The product-sum operating circuitry is configured to perform a product-sum operation based on the items of information indicative of the input, the weight, and the bit width, stored in the memory.
    Type: Application
    Filed: March 4, 2019
    Publication date: January 23, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Asuka MAKI, Daisuke Miyashita, Kengo Nakata, Fumihiko Tachibana, Jun Deguchi, Shinichi Sasaki
  • Patent number: 10505108
    Abstract: A memcapacitor according to an embodiment includes a first electrode, a first dielectric layer provided on the first electrode, a plurality of variable resistance portions provided separately from each other on the first dielectric layer, a second dielectric layer provided on the first dielectric layer and between the variable resistance portions, and a second electrode provided on the variable resistance portions and the second dielectric layer. Each of the variable resistance portions is formed of a material that allows diffusion of metal atoms constituting the second electrode to inside of the variable resistance portion, and the second dielectric layer is formed of a material that prevents diffusion of the metal atoms constituting the second electrode to inside of the second dielectric layer.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: December 10, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takao Marukame, Jun Deguchi, Yoshifumi Nishi, Masamichi Suzuki, Fumihiko Tachibana, Makoto Morimoto, Yuichiro Mitani
  • Publication number: 20190294957
    Abstract: An arithmetic device includes: an arithmetic circuit that includes arithmetic elements connected in series, and sequentially performs multiple repetitions of arithmetic processing, wherein each of the arithmetic elements receives a first time signal and a second time signal, and generates a third time signal and a fourth time signal obtained by delaying the first and second time signals by a time corresponding to a weight coefficient and input data; a converter that converts a difference between the third and fourth time signals output from the arithmetic circuit into an analog signal or a digital signal for every multiple repetition of arithmetic processing; an integrator that integrates analog signals or digital signals converted by the converter; and a comparator that compares the integration result by the integrator with a reference value.
    Type: Application
    Filed: September 5, 2018
    Publication date: September 26, 2019
    Inventor: Fumihiko Tachibana
  • Publication number: 20190074063
    Abstract: According to one embodiment, a transmitter includes a 1st circuit configured to execute a 1st band limitation by waveform shaping in a time region with respect to 1st data relating to a 1st channel to generate a 1st signal; a 2nd circuit configured to execute a 2nd band limitation by the waveform shaping in the time region with respect to 2nd data relating to a 2nd channel to generate a 2nd signal; a 3rd circuit configured to generate a 3rd signal based on the 1st signal and a 1st frequency relating to the 1st channel; a 4th circuit configured to generate a 4th signal based on the 2nd signal and a 2nd frequency relating to the 2nd channel; and a 5th circuit configured to generate a 5th signal by multiplexing the 3rd signal and the 4th signal.
    Type: Application
    Filed: March 13, 2018
    Publication date: March 7, 2019
    Inventors: Yuta Tsubouchi, Jun Deguchi, Daisuke Miyashita, Makoto Morimoto, Junji Wadatsumi, Fumihiko Tachibana, Yuji Satoh, Takashi Toi
  • Publication number: 20180082168
    Abstract: A memcapacitor according to an embodiment includes a first electrode, a first dielectric layer provided on the first electrode, a plurality of variable resistance portions provided separately from each other on the first dielectric layer, a second dielectric layer provided on the first dielectric layer and between the variable resistance portions, and a second electrode provided on the variable resistance portions and the second dielectric layer. Each of the variable resistance portions is formed of a material that allows diffusion of metal atoms constituting the second electrode to inside of the variable resistance portion, and the second dielectric layer is formed of a material that prevents diffusion of the metal atoms constituting the second electrode to inside of the second dielectric layer.
    Type: Application
    Filed: February 28, 2017
    Publication date: March 22, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takao MARUKAME, Jun DEGUCHI, Yoshifumi NISHI, Masamichi SUZUKI, Fumihiko TACHIBANA, Makoto MORIMOTO, Yuichiro MITANI
  • Patent number: 9531977
    Abstract: According to an embodiment, a semiconductor integrated circuit includes an amplification unit, a comparison unit and a control unit. The amplification unit is configured to amplify a pixel value with an amplification factor that is set in a variable manner, the pixel value being according to an intensity of light irradiated on a pixel. The comparison unit is configured to compare an output value given by the amplification unit and a reference value. The control unit is configured to cause the amplification factor to be higher than a present amplification factor, only when the output value given by the amplification unit is not saturated even where the amplification factor is caused to be higher than the present amplification factor, based on the comparison result of the comparison unit.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: December 27, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jun Deguchi, Daisuke Miyashita, Makoto Morimoto, Fumihiko Tachibana
  • Publication number: 20150237281
    Abstract: According to an embodiment, a semiconductor integrated circuit includes an amplification unit, a comparison unit and a control unit. The amplification unit is configured to amplify a pixel value with an amplification factor that is set in a variable manner, the pixel value being according to an intensity of light irradiated on a pixel. The comparison unit is configured to compare an output value given by the amplification unit and a reference value. The control unit is configured to cause the amplification factor to be higher than a present amplification factor, only when the output value given by the amplification unit is not saturated even where the amplification factor is caused to be higher than the present amplification factor, based on the comparison result of the comparison unit.
    Type: Application
    Filed: September 10, 2014
    Publication date: August 20, 2015
    Inventors: Jun Deguchi, Daisuke Miyashita, Makoto Morimoto, Fumihiko Tachibana
  • Publication number: 20140070074
    Abstract: According to one embodiment, a semiconductor integrated circuit includes: a CDS (Correlated Double Sampling) circuit; and an adjustment voltage generator. The CDS circuit has a first capacitor and a second capacitor. The first capacitor has a first electrode and a second electrode. The second capacitor has a third electrode and a fourth electrode. The CDS circuit is configured to hold a voltage corresponding to light intensity as a signal voltage. The adjustment voltage generator is configured to supply an adjustment voltage to the CDS circuit. A first signal voltage is supplied to the first electrode, and a second signal voltage is supplied to the third electrode. The second electrode and the fourth electrode are commonly connected and supplied with the adjustment voltage from the adjustment voltage generator.
    Type: Application
    Filed: February 28, 2013
    Publication date: March 13, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Fumihiko TACHIBANA, Jun DEGUCHI
  • Patent number: 8451672
    Abstract: A memory cell stores therein data, a dummy cell replicates an operation of the memory cell, a write control unit makes the dummy cell to perform writing in synchronization with write timing of the memory cell, and a row decoder performs opening and closing of a word line that performs a row selection of the memory cell based on a monitored result of a write condition of the dummy cell.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: May 28, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Fumihiko Tachibana
  • Patent number: 8400821
    Abstract: According to one embodiment, a dummy cell simulates an operation of a memory cell. A main dummy bit line transmits a signal read out from the dummy cell. An inverter makes a sense amplifier circuit to operate based on a potential of the main dummy bit line. n (n is a positive integer) number of auxiliary dummy bit lines are provided. A switching element connects at least one of the n number of auxiliary dummy bit lines to the main dummy bit line.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: March 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Fumihiko Tachibana
  • Publication number: 20120127784
    Abstract: According to one embodiment, a dummy cell simulates an operation of a memory cell. A main dummy bit line transmits a signal read out from the dummy cell. An inverter makes a sense amplifier circuit to operate based on a potential of the main dummy bit line. n (n is a positive integer) number of auxiliary dummy bit lines are provided. A switching element connects at least one of the n number of auxiliary dummy bit lines to the main dummy bit line.
    Type: Application
    Filed: September 21, 2011
    Publication date: May 24, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Fumihiko TACHIBANA
  • Publication number: 20120096323
    Abstract: According to one embodiment, a certain amount of data is held in the memory cells, and after a state of the data held in the memory cell is transferred into an indefinite state, data autonomously held in the memory cell is read, and a change of the threshold voltage of transistors is diagnosed on the basis of the distribution of the data autonomously held in the memory cell.
    Type: Application
    Filed: March 22, 2011
    Publication date: April 19, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Fumihiko TACHIBANA
  • Publication number: 20120014191
    Abstract: A semiconductor memory device of an embodiment includes memory cells 2, a write-back determining unit 7, and a read controller 8. Each memory cell 2 is capable of writing and reading through different paths. The write-back determining unit 7 determines whether or not to perform the write-back for a non-selected column, at the time of the write for a selected column. On the basis of the determination result of the write-back determining unit 7, the read controller 8 controls the read of the data used in the write-back for the non-selected column.
    Type: Application
    Filed: July 12, 2011
    Publication date: January 19, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Azuma SUZUKI, Fumihiko TACHIBANA, Tomoaki YABE
  • Publication number: 20120008430
    Abstract: According to the embodiments, a memory cell stores therein data, a dummy cell replicates an operation of the memory cell, a write control unit makes the dummy cell to perform writing in synchronization with write timing of the memory cell, and a row decoder performs opening and closing of a word line that performs a row selection of the memory cell based on a monitored result of a write condition of the dummy cell.
    Type: Application
    Filed: March 17, 2011
    Publication date: January 12, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Fumihiko TACHIBANA
  • Publication number: 20100231273
    Abstract: A semiconductor device has a first MOS transistor being connected between a signal terminal and a first power supply line and having a gate connected to a second power supply line; a first capacitive element connected between the signal terminal and the second power supply line; a second MOS transistor being connected between the signal terminal and the second power supply line and having a gate connected to a first terminal; a third MOS transistor being connected between the first power supply line and the first terminal and having a gate connected to the second power supply line; a fourth MOS transistor being connected between the first terminal and a second terminal and having a gate connected to the second power supply line; a second capacitive element connected between the first power supply line and the second terminal; and a fifth MOS transistor being connected between the second terminal and the second power supply line.
    Type: Application
    Filed: August 13, 2009
    Publication date: September 16, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Fumihiko TACHIBANA
  • Patent number: 7605601
    Abstract: A semiconductor integrated circuit device, has a semiconductor substrate; and a first transistor of a first conductivity type and a second transistor of the first conductivity type, the transistors being connected in series between a first power supply line and a first substrate well provided on the semiconductor substrate, the semiconductor integrated circuit device further comprising a first transistor of a second conductivity type and a second transistor of the second conductivity type, the transistors being connected in series between the second power supply line and a second substrate well provided on the semiconductor substrate.
    Type: Grant
    Filed: April 18, 2008
    Date of Patent: October 20, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fumihiko Tachibana, Takahiro Yamashita