Patents by Inventor Fumihiro Kohno
Fumihiro Kohno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7248520Abstract: A semiconductor memory having memory cells each storing first data and second data in a memory cell array arranged in a column direction; a plurality of word lines connected to the memory cells in a row direction; and first and second bit lines, to which the first and second data are respectively read out, in the column direction. When one of the first and second bit lines changes from a first potential to a second potential lower than the first potential after data read out, the potential of the other bit line is changed from the second to the first potential, and if the electric potential of the selected bit line changes from the first to the second potential when data is read out, the other bit line is selected when the data is next read out, and, if the electric potential of the selected bit line maintains the first potential, the selected bit line is maintained selected even when the data is to be read out next.Type: GrantFiled: December 9, 2005Date of Patent: July 24, 2007Assignee: Kabushiki Kaisha ToshibaInventor: Fumihiro Kohno
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Publication number: 20060203583Abstract: According to the present invention, there is provided a semiconductor memory having: a memory cell array in which a plurality of memory cells each holding data made up of first data and second data are arranged at least along a column direction; a plurality of word lines running along a row direction in the memory cell array, and connected to the memory cells; a first bit line which runs along the column direction in the memory cell array and is connected to the memory cells, and to which the first data is read out from the memory cell when the data is read out from the memory cell; a second bit line which runs along the column direction in the memory cell array and is connected to the memory cells, and to which the second data is read out from the memory cell when the data is read out from the memory cell; a bit line precharge unit which, when detecting that an electric potential of one of the first and second bit lines changes from a first potential to a second potential lower than the first potential afterType: ApplicationFiled: December 9, 2005Publication date: September 14, 2006Applicant: Kabushiki Kaisha ToshibaInventor: Fumihiro Kohno
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Patent number: 6898100Abstract: A data memory circuit having divided several cache lines storing data, and several entries, and a tag circuit, are provided. The tag circuit having an array of an associative memory including a memory cell circuit having several memory cells storing address corresponding to the data stored in the data memory circuit and divided several rows, and a comparator circuit comparing the address stored in the memory cell circuit with input address, the comparator circuit comparing the address stored in divided several rows of the memory cell circuit with the input address concurrently in each of divided rows storing the address, and generating a cache hit/miss determination signal based on the comparative result of each row, the hit/miss determination signal being supplied to the data memory circuit.Type: GrantFiled: December 17, 2003Date of Patent: May 24, 2005Assignee: Kabushiki Kaisha ToshibaInventor: Fumihiro Kohno
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Publication number: 20050083719Abstract: A data memory circuit having divided several cache lines storing data, and several entries, and a tag circuit, are provided. The tag circuit having an array of an associative memory including a memory cell circuit having several memory cells storing address corresponding to the data stored in the data memory circuit and divided several rows, and a comparator circuit comparing the address stored in the memory cell circuit with input address, the comparator circuit comparing the address stored in divided several rows of the memory cell circuit with the input address concurrently in each of divided rows storing the address, and generating a cache hit/miss determination signal based on the comparative result of each row, the hit/miss determination signal being supplied to the data memory circuit.Type: ApplicationFiled: December 17, 2003Publication date: April 21, 2005Inventor: Fumihiro Kohno
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Patent number: 6847579Abstract: A semiconductor memory device includes a memory cell array having a plurality of memory cells. The memory cells are arranged at intersections between a plurality of word lines and a plurality of bit lines. The semiconductor memory device also includes a row decoder section located adjacent to the memory cell array. The row decoder section has a plurality of decoder circuits which selectively drive the word lines. The semiconductor memory device further includes a control circuit section located adjacent to the row decoder section. The control circuit section has at least one control circuit whose part is arranged in the row decoder section.Type: GrantFiled: April 29, 2002Date of Patent: January 25, 2005Assignees: Kabushiki Kaisha Toshiba, Fujitsu LimitedInventors: Fumihiro Kohno, Toshimi Ikeda
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Patent number: 6650590Abstract: One (first level shift circuit) of first and second level shift circuits is provided in a local word-drive-line driving circuit located near memory cell arrays. The second level shift circuit is provided in a global word-drive-line driving circuit located remote from the memory cell arrays.Type: GrantFiled: March 22, 2002Date of Patent: November 18, 2003Assignees: Kabushiki Kaisha Toshiba, Fujitsu LimitedInventors: Tsuneo Inaba, Fumihiro Kohno, Kenji Tsuchida, Toshimi Ikeda
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Patent number: 6560163Abstract: The present invention provides a DRAM in which a first repetitive unit including a plurality of decoders for selecting a plurality of word lines and a second repetitive unit having the same arrangement as that of the first repetitive unit are arranged symmetrically with respect a boundary region therebetween. The first and second repetitive units have a wire and a contact located on a boundary portion therebetween in common.Type: GrantFiled: January 9, 2002Date of Patent: May 6, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Hironobu Akita, Shinichiro Shiratake, Fumihiro Kohno
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Patent number: 6538955Abstract: There are provided a plurality of CMOS configured pre-driver circuits, wherein an increased voltage obtained by increasing a power voltage is applied to a source of each P-channel transistor, and a word line driver circuit each having a P-channel transistor and an N-channel transistor to which an output of the pre-driver circuit is inputted. The source of each N-channel transistor in the plurality of pre-driver circuits is connected in common to that of each N-channel transistor in the word line driver circuit, and a source-drain path of an N-channel transistor for voltage alleviation is connected between this source common node and a node of a grounding voltage. The increased voltage is applied to a gate of the N-channel transistor for voltage alleviation.Type: GrantFiled: July 17, 2001Date of Patent: March 25, 2003Assignee: Kabushiki Kaisha ToshibaInventor: Fumihiro Kohno
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Publication number: 20030048688Abstract: A semiconductor memory device includes a memory cell array having a plurality of memory cells. The memory cells are arranged at intersections between a plurality of word lines and a plurality of bit lines. The semiconductor memory device also includes a row decoder section located adjacent to the memory cell array. The row decoder section has a plurality of decoder circuits which selectively drive the word lines. The semiconductor memory device further includes a control circuit section located adjacent to the row decoder section. The control circuit section has at least one control circuit whose part is arranged in the row decoder section.Type: ApplicationFiled: April 29, 2002Publication date: March 13, 2003Inventors: Fumihiro Kohno, Toshimi Ikeda
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Publication number: 20020141277Abstract: One (first level shift circuit) of first and second level shift circuits is provided in a local word-drive-line driving circuit located near memory cell arrays. The second level shift circuit is provided in a global word-drive-line driving circuit located remote from the memory cell arrays.Type: ApplicationFiled: March 22, 2002Publication date: October 3, 2002Applicant: Kabushiki Kaisha ToshibaInventors: Tsuneo Inaba, Fumihiro Kohno, Kenji Tsuchida, Toshimi Ikeda
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Patent number: 6452833Abstract: A BL kicker circuit includes first capacitors each of which is connected at one end to a first bit line which is one of bit lines of a corresponding pair and commonly connected at the other end, second capacitors each of which is connected at one end to a second bit line which is the other one of the bit lines of a corresponding pair and commonly connected at the other end, a first driver circuit having an output node for a first signal connected to the common connection node of the other ends of the first capacitors, a second drive circuit having an output node for a second signal connected to the common connection node of the other ends of the second capacitors, and a switch circuit used as an equalizing circuit connected between the output node for the first signal and the output node for the second signal.Type: GrantFiled: February 2, 2001Date of Patent: September 17, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Hironobu Akita, Kenji Tsuchida, Fumihiro Kohno
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Publication number: 20020057589Abstract: The present invention provides a DRAM in which a first repetitive unit including a plurality of decoders for selecting a plurality of word lines and a second repetitive unit having the same arrangement as that of the first repetitive unit are arranged symmetrically with respect a boundary region therebetween. The first and second repetitive units have a wire and a contact located on a boundary portion therebetween in common.Type: ApplicationFiled: January 9, 2002Publication date: May 16, 2002Applicant: Kabushiki Kaisha ToshibaInventors: Hironobu Akita, Shinichiro Shiratake, Fumihiro Kohno
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Patent number: 6362999Abstract: The present invention provides a DRAM in which a first repetitive unit including a plurality of decoders for selecting a plurality of word lines and a second repetitive unit having the same arrangement as that of the first repetitive unit are arranged symmetrically with respect a boundary region therebetween. The first and second repetitive units have a wire and a contact located on a boundary portion therebetween in common.Type: GrantFiled: January 30, 2001Date of Patent: March 26, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Hironobu Akita, Shinichiro Shiratake, Fumihiro Kohno
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Publication number: 20020024876Abstract: There are provided a plurality of CMOS configured pre-driver circuits, wherein an increased voltage obtained by increasing a power voltage is applied to a source of each P-channel transistor, and a word line driver circuit each having a P-channel transistor and an N-channel transistor to which an output of the pre-driver circuit is inputted. The source of each N-channel transistor in the plurality of pre-driver circuits is connected in common to that of each N-channel transistor in the word line driver circuit, and a source-drain path of an N-channel transistor for voltage alleviation is connected between this source common node and a node of a grounding voltage. The increased voltage is applied to a gate of the N-channel transistor for voltage alleviation.Type: ApplicationFiled: July 17, 2001Publication date: February 28, 2002Inventor: Fumihiro Kohno
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Publication number: 20010012214Abstract: A BL kicker circuit includes first capacitors each of which is connected at one end to a first bit line which is one of bit lines of a corresponding pair and commonly connected at the other end, second capacitors each of which is connected at one end to a second bit line which is the other one of the bit lines of a corresponding pair and commonly connected at the other end, a first driver circuit having an output node for a first signal connected to the common connection node of the other ends of the first capacitors, a second drive circuit having an output node for a second signal connected to the common connection node of the other ends of the second capacitors, and a switch circuit used as an equalizing circuit connected between the output node for the first signal and the output node for the second signal.Type: ApplicationFiled: February 2, 2001Publication date: August 9, 2001Inventors: Hironobu Akita, Kenji Tsuchida, Fumihiro Kohno
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Patent number: 6269047Abstract: A semiconductor memory device comprising a plurality of row decoders, each having a precharge circuit connected to receive a precharge signal and a decode circuit connected to receive address signals. A level-shifted precharge signal is input to the precharge circuits.Type: GrantFiled: July 17, 2000Date of Patent: July 31, 2001Assignee: Kabushiki Kaisha ToshibaInventor: Fumihiro Kohno
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Publication number: 20010002883Abstract: The present invention provides a DRAM in which a first repetitive unit including a plurality of decoders for selecting a plurality of word lines and a second repetitive unit having the same arrangement as that of the first repetitive unit are arranged symmetrically with respect a boundary region therebetween. The first and second repetitive units have a wire and a contact located on a boundary portion therebetween in common.Type: ApplicationFiled: January 30, 2001Publication date: June 7, 2001Inventors: Hironobu Akita, Shinichiro Shiratake, Fumihiro Kohno
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Patent number: 6212090Abstract: The present invention provides a DRAM in which a first repetitive unit including a plurality of decoders for selecting a plurality of word lines and a second repetitive unit having the same arrangement as that of the first repetitive unit are arranged symmetrically with respect a boundary region therebetween. The first and second repetitive units have a wire and a contact located on a boundary portion therebetween in common.Type: GrantFiled: December 23, 1999Date of Patent: April 3, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Hironobu Akita, Shinichiro Shiratake, Fumihiro Kohno
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Patent number: 6160752Abstract: A semiconductor memory device comprising a plurality of row decoders, each having a precharge circuit connected to receive a precharge signal and a decode circuit connected to receive address signals. A level-shifted precharge signal is input to the precharge circuits.Type: GrantFiled: December 2, 1999Date of Patent: December 12, 2000Assignee: Kabushiki Kaisha ToshibaInventor: Fumihiro Kohno
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Patent number: 6141291Abstract: A semiconductor memory device comprising a plurality of row decoders, each having a precharge circuit connected to receive a precharge signal and a decode circuit connected to receive address signals. A level-shifted precharge signal is input to the precharge circuits.Type: GrantFiled: October 25, 1999Date of Patent: October 31, 2000Assignee: Kabushiki Kaisha ToshibaInventor: Fumihiro Kohno