Patents by Inventor Fumihiro Kohno

Fumihiro Kohno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device with high data read rate
    Patent number: 6125071
    Abstract: A memory cell array has a plurality of memory cells arranged in a matrix. A row decoder has a multiple selection period when a plurality of word lines are simultaneously selected and word lines are sequentially selected. A plurality of sense amplifiers are arranged for each bit line. These sense amplifiers are selectively connected to the bit lines by switch circuits formed on the bit lines. A sense amplifier receives data from memory cells on one bit line through a switch circuit. A plurality of word lines are simultaneously selected and sequentially set at a high level. Data from memory cells on one bit line are sequentially received by the sense amplifier and amplified.
    Type: Grant
    Filed: April 22, 1999
    Date of Patent: September 26, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fumihiro Kohno, Haruki Toda
  • Semiconductor memory device having level-shifted precharge signal
    Patent number: 6044035
    Abstract: A semiconductor memory device comprising a plurality of row decoders, each having a precharge circuit connected to receive a precharge signal and a decode circuit connected to receive address signals. A level-shifted precharge signal is input to the precharge circuits.
    Type: Grant
    Filed: October 9, 1998
    Date of Patent: March 28, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Fumihiro Kohno
  • Semiconductor memory device, method of laying out semiconductor memory device, method of driving semiconductor pattern of semiconductor device
    Patent number: 6041013
    Abstract: A semiconductor memory device adapted to enhanced functional features and a large memory capacity. The semiconductor memory device includes a semiconductor chip divided into 9 regions B1 through B9 having an identical area, in a 3.times.3 pattern. A main control block is arranged at least in a central region B9 and memory blocks are arranged respectively in the peripheral regions B1 through B8 of the 9 regions. Each of the memory blocks is controlled by the main control block and includes a data input/output circuit and a memory control circuit.
    Type: Grant
    Filed: April 13, 1999
    Date of Patent: March 21, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Fumihiro Kohno
  • Arrangement of memory blocks and pads
    Patent number: 5943285
    Abstract: A semiconductor memory device adapted to enhanced functional features and a large memory capacity. The semiconductor memory device includes a semiconductor chip divided into 9 regions B1 through B9 having an identical area, in a 3.times.3 pattern. A main control block is arranged at least in a central region B9 and memory blocks are arranged respectively in the peripheral regions B1 through B8 of the 9 regions. Each of the memory blocks is controlled by the main control block and includes a data input/output circuit and a memory control circuit.
    Type: Grant
    Filed: August 1, 1997
    Date of Patent: August 24, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Fumihiro Kohno
  • Semiconductor memory device having level-shifted precharge signal
    Patent number: 5838629
    Abstract: A semiconductor memory device comprising a plurality of row decoders, each having a precharge circuit connected to receive a precharge signal and a decode circuit connected to receive address signals. A level-shifted precharge signal is input to the precharge circuits.
    Type: Grant
    Filed: August 6, 1997
    Date of Patent: November 17, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Fumihiro Kohno
  • Semiconductor memory device having noise killer circuit
    Patent number: 5825714
    Abstract: A semiconductor memory device comprising a plurality of row decoders, each having a precharge circuit connected to receive a precharge signal and a decode circuit connected to receive address signals. A level-shifted precharge signal is input to the precharge circuits.
    Type: Grant
    Filed: January 27, 1995
    Date of Patent: October 20, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Fumihiro Kohno
  • Semiconductor memory device having level-shifted precharge signal
    Patent number: 5793695
    Abstract: A semiconductor memory device comprising a plurality of row decoders, each having a precharge circuit connected to receive a precharge signal and a decode circuit connected to receive address signals. A level-shifted precharge signal is input to the precharge circuits.
    Type: Grant
    Filed: August 14, 1996
    Date of Patent: August 11, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Fumihiro Kohno