Patents by Inventor Fuminori Ito
Fuminori Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230334487Abstract: A settlement system includes code display section and mobile terminal. A first information and remittance destination information are displayed as specific information code on code display section. Code display section has memory for storing second information for authenticating first information, and antenna coil for receiving radio waves, generating electromotive force, supplying electromotive force to memory, and transmitting second information recorded memory. Mobile terminal has imaging unit for imaging information code, transceiver for transmitting and receiving response to radio waves, imaging control unit for imaging information code, transmitter control unit for transmitting radio waves to transceiver, and processing control unit performs settlement processing using remittance destination information read from specific information code when authentication using first information read from specific information code and second information received by transceiver as response to radio wave is successful.Type: ApplicationFiled: September 24, 2021Publication date: October 19, 2023Applicant: DENSO WAVE INCORPORATEDInventors: Chiaki BABA, Fuminori ITO, Mieko FUKATSU
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Patent number: 9236430Abstract: The deposition rate of a porous insulation film is increased, and the film strength of the porous insulation film is improved. Two or more organic siloxane raw materials each having a cyclic SiO structure as a main skeleton thereof, and having mutually different structures, are vaporized, and transported with a carrier gas to a reactor (chamber), and an oxidant gas including an oxygen atom is added thereto. Thus, a porous insulation film is formed by a plasma CVD (Chemical Vapor Deposition) method or a plasma polymerization method in the reactor (chamber). In the step, the ratio of the flow rate of the added oxidant gas to the flow rate of the carrier gas is more than 0 and 0.08 or less.Type: GrantFiled: May 1, 2015Date of Patent: January 12, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hironori Yamamoto, Fuminori Ito, Yoshihiro Hayashi
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Publication number: 20150236091Abstract: The deposition rate of a porous insulation film is increased, and the film strength of the porous insulation film is improved. Two or more organic siloxane raw materials each having a cyclic SiO structure as a main skeleton thereof, and having mutually different structures, are vaporized, and transported with a carrier gas to a reactor (chamber), and an oxidant gas including an oxygen atom is added thereto. Thus, a porous insulation film is formed by a plasma CVD (Chemical Vapor Deposition) method or a plasma polymerization method in the reactor (chamber). In the step, the ratio of the flow rate of the added oxidant gas to the flow rate of the carrier gas is more than 0 and 0.08 or less.Type: ApplicationFiled: May 1, 2015Publication date: August 20, 2015Inventors: Hironori YAMAMOTO, Fuminori ITO, Yoshihiro HAYASHI
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Patent number: 9034740Abstract: The deposition rate of a porous insulation film is increased, and the film strength of the porous insulation film is improved. Two or more organic siloxane raw materials each having a cyclic SiO structure as a main skeleton thereof, and having mutually different structures, are vaporized, and transported with a carrier gas to a reactor (chamber), and an oxidant gas including an oxygen atom is added thereto. Thus, a porous insulation film is formed by a plasma CVD (Chemical Vapor Deposition) method or a plasma polymerization method in the reactor (chamber). In the step, the ratio of the flow rate of the added oxidant gas to the flow rate of the carrier gas is more than 0 and 0.08 or less.Type: GrantFiled: May 6, 2013Date of Patent: May 19, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hironori Yamamoto, Fuminori Ito, Yoshihiro Hayashi
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Patent number: 8937023Abstract: A method includes forming an insulating film over a substrate by introducing a cyclic siloxane compound having a cyclic siloxane as a skeleton and having at least one volatile hydrocarbon group bonded to a side chain, and a silicon-containing compound into a plasma, and converting the insulating film to a porous insulating film by adding energy to the insulating film. The silicon-containing compound is decomposed using less energy as compared with the skeleton of the cyclic siloxane compound, the volatile hydrocarbon group, and the bond between the cyclic siloxane compound and the volatile hydrocarbon group.Type: GrantFiled: February 1, 2012Date of Patent: January 20, 2015Assignee: Renesas Electronics CorporationInventors: Fuminori Ito, Yoshihiro Hayashi
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Patent number: 8790785Abstract: A method of forming a porous insulation film uses an organic silica material gas having a 3-membered SiO cyclic structure and a 4-membered SiO cyclic structure, or an organic silica material gas having a 3-membered SiO cyclic structure and a straight-chain organic silica structure, and uses a plasma reaction in the filming process. A porous interlevel dielectric film having a higher strength and a higher adhesive property can be obtained.Type: GrantFiled: July 23, 2007Date of Patent: July 29, 2014Assignee: Renesas Electronics CorporationInventors: Hironori Yamamoto, Fuminori Ito, Munehiro Tada, Yoshihiro Hayashi
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Patent number: 8598706Abstract: A method for forming an interlayer dielectric film by a plasma CVD method, including turning off a radio frequency power and purging with an inert gas simultaneously.Type: GrantFiled: September 17, 2008Date of Patent: December 3, 2013Assignee: Renesas Electronics CorporationInventors: Hironori Yamamoto, Fuminori Ito, Yoshihiro Hayashi
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Patent number: 8592283Abstract: A semiconductor device manufacturing method for manufacturing a semiconductor device having a transistor mounted in a wiring of a plural-layer structure includes in manufacturing the semiconductor device that is formed on a semiconductor element and includes a barrier insulating film, a porous interlayer insulating film, a wiring, a via plug formed by embedding a metal wiring material in a wiring trench, and a via hole formed in the porous interlayer insulating film, irradiating an electron beam or an ultraviolet ray onto at least a portion of the porous interlayer insulating film before forming an opening in the barrier insulating film.Type: GrantFiled: August 30, 2011Date of Patent: November 26, 2013Assignee: Renesas Electronics CorporationInventors: Fuminori Ito, Yoshihiro Hayashi, Tsuneo Takeuchi
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Patent number: 8592303Abstract: There are provided with a wiring structure and a method for manufacturing the same wherein in a wiring structure of multi-layered wiring in which a metal wiring is formed on a substrate forming a semiconductor element thereby obtaining connection of the element, no damage to insulation property between the abutting wirings by occurrence of leakage current and no deterioration of insulation resistance property between the abutting wirings are achieved in case that fine metal wiring is formed in a porous insulation film. The insulation barrier layer 413 is formed between an interlayer insulation film and the metal wiring, in the metal wiring structure on the substrate forming the semiconductor element. The insulation barrier layer enables to reduce leakage current between the abutting wirings and to elevate the insulation credibility.Type: GrantFiled: March 1, 2010Date of Patent: November 26, 2013Assignees: Renesas Electronics Corporation, NEC CorporationInventors: Munehiro Tada, Yoshihiro Hayashi, Yoshimichi Harada, Fuminori Ito, Hiroto Ohtake, Tatsuya Usami
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Publication number: 20130299952Abstract: The deposition rate of a porous insulation film is increased, and the film strength of the porous insulation film is improved. Two or more organic siloxane raw materials each having a cyclic SiO structure as a main skeleton thereof, and having mutually different structures, are vaporized, and transported with a carrier gas to a reactor (chamber), and an oxidant gas including an oxygen atom is added thereto. Thus, a porous insulation film is formed by a plasma CVD (Chemical Vapor Deposition) method or a plasma polymerization method in the reactor (chamber). In the step, the ratio of the flow rate of the added oxidant gas to the flow rate of the carrier gas is more than 0 and 0.08 or less.Type: ApplicationFiled: May 6, 2013Publication date: November 14, 2013Applicant: Renesas Electronics CorporationInventors: Hironori YAMAMOTO, Fuminori ITO, Yoshihiro HAYASHI
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Patent number: 8377823Abstract: A method of forming a semiconductor device includes forming a trench on a porous insulating film, placing a chemical material including a structure comprising —Si—O— including vinyl group on a surface of the porous insulating film or in the porous insulating film, and performing polymerization of the chemical material to provide a dielectric film having a density higher than that of porous insulating film on the surface of the trench. The structure may be a structure defined by a formula 1.Type: GrantFiled: February 9, 2011Date of Patent: February 19, 2013Assignee: Renesas Electronics CorporationInventors: Masayoshi Tagami, Fuminori Ito
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Patent number: 8278763Abstract: The present invention provides a multilayer wiring technology by which high adhesiveness and high insulation reliability between wirings are obtained, while maintaining effective low capacitance between wirings. A semiconductor device is characterized in that a first insulating film is an insulating film formed of at least one layer which contains a siloxane structure containing silicon, oxygen and carbon; the siloxane structure in the inner part of the first insulating film contains a larger number of carbon atoms than the number of silicon atoms; and a modified layer which containing a smaller number of carbon atoms and a larger number of oxygen atoms per unit volume than the inner part of the first insulating film is formed on at least one of an interface between the first insulating film and the metal and an interface between the first insulating film and a second insulating film.Type: GrantFiled: September 21, 2011Date of Patent: October 2, 2012Assignee: NEC CorporationInventors: Munehiro Tada, Hiroto Ohtake, Fuminori Ito, Yoshihiro Hayashi, Hironori Yamamoto
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Publication number: 20120135611Abstract: A method includes forming an insulating film over a substrate by introducing a cyclic siloxane compound having a cyclic siloxane as a skeleton and having at least one volatile hydrocarbon group bonded to a side chain, and a silicon-containing compound into a plasma, and converting the insulating film to a porous insulating film by adding energy to the insulating film. The silicon-containing compound is decomposed using less energy as compared with the skeleton of the cyclic siloxane compound, the volatile hydrocarbon group, and the bond between the cyclic siloxane compound and the volatile hydrocarbon group.Type: ApplicationFiled: February 1, 2012Publication date: May 31, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Fuminori ITO, Yoshihiro HAYASHI
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Patent number: 8133821Abstract: A method includes forming an insulating film over a substrate by introducing a cyclic siloxane compound having a cyclic siloxane as a skeleton and having at least one volatile hydrocarbon group bonded to a side chain, and a silicon-containing compound into a plasma, and converting the insulating film to a porous insulating film by adding energy to the insulating film. The silicon-containing compound is decomposed using less energy as compared with the skeleton of the cyclic siloxane compound, the volatile hydrocarbon group, and the bond between the cyclic siloxane compound and the volatile hydrocarbon group.Type: GrantFiled: November 18, 2009Date of Patent: March 13, 2012Assignee: Renesas Electronics CorporationInventors: Fuminori Ito, Yoshihiro Hayashi
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Publication number: 20120013023Abstract: The present invention provides a multilayer wiring technology by which high adhesiveness and high insulation reliability between wirings are obtained, while maintaining effective low capacitance between wirings. A semiconductor device is characterized in that a first insulating film is an insulating film formed of at least one layer which contains a siloxane structure containing silicon, oxygen and carbon; the siloxane structure in the inner part of the first insulating film contains a larger number of carbon atoms than the number of silicon atoms; and a modified layer which containing a smaller number of carbon atoms and a larger number of oxygen atoms per unit volume than the inner part of the first insulating film is formed on at least one of an interface between the first insulating film and the metal and an interface between the first insulating film and a second insulating film.Type: ApplicationFiled: September 21, 2011Publication date: January 19, 2012Applicant: NEC CORPORATIONInventors: Munehiro TADA, Hiroto OHTAKE, Fuminori ITO, Yoshihiro HAYASHI, Hironori YAMAMOTO
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Publication number: 20110318926Abstract: A semiconductor device manufacturing method for manufacturing a semiconductor device having a transistor mounted in a wiring of a plural-layer structure includes in manufacturing the semiconductor device that is formed on a semiconductor element and includes a barrier insulating film, a porous interlayer insulating film, a wiring, a via plug formed by embedding a metal wiring material in a wiring trench, and a via hole formed in the porous interlayer insulating film, irradiating an electron beam or an ultraviolet ray onto at least a portion of the porous interlayer insulating film before forming an opening in the barrier insulating film.Type: ApplicationFiled: August 30, 2011Publication date: December 29, 2011Applicant: NEC CORPORATIONInventors: Fuminori Ito, Yoshihiro Hayashi, Tsuneo Takeuchi
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Patent number: 8043957Abstract: The present invention provides a multilayer wiring technology by which high adhesiveness and high insulation reliability between wirings are obtained, while maintaining effective low capacitance between wirings. A semiconductor device is characterized in that a first insulating film is an insulating film formed of at least one layer which contains a siloxane structure containing silicon, oxygen and carbon; the siloxane structure in the inner part of the first insulating film contains a larger number of carbon atoms than the number of silicon atoms; and a modified layer which containing a smaller number of carbon atoms and a larger number of oxygen atoms per unit volume than the inner part of the first insulating film is formed on at least one of an interface between the first insulating film and the metal and an interface between the first insulating film and a second insulating film.Type: GrantFiled: May 16, 2007Date of Patent: October 25, 2011Assignee: NEC CorporationInventors: Munehiro Tada, Hiroto Ohtake, Fuminori Ito, Yoshihiro Hayashi, Hironori Yamamoto
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Patent number: 8039921Abstract: A semiconductor device with a high-strength porous modified layer having a pore size of 1 nm or less, which is formed, in a multilayer wiring forming process, by forming a via hole and a wiring trench in a via interlayer insulating film and a wiring interlayer insulting film and then irradiating an electron beam or an ultraviolet ray onto the opening side walls.Type: GrantFiled: September 15, 2006Date of Patent: October 18, 2011Assignee: NEC CorporationInventors: Fuminori Ito, Yoshihiro Hayashi, Tsuneo Takeuchi
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Publication number: 20110198754Abstract: A method of forming a semiconductor device includes forming a trench on a porous insulating film, placing a chemical material including a structure comprising —Si—O— including vinyl group on a surface of the porous insulating film or in the porous insulating film, and performing polymerization of the chemical material to provide a dielectric film having a density higher than that of porous insulating film on the surface of the trench. The structure may be a structure defined by a formula 1.Type: ApplicationFiled: February 9, 2011Publication date: August 18, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Masayoshi Tagami, Fuminori Ito
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Publication number: 20100151675Abstract: There are provided with a wiring structure and a method for manufacturing the same wherein in a wiring structure of multi-layered wiring in which a metal wiring is formed on a substrate forming a semiconductor element thereby obtaining connection of the element, no damage to insulation property between the abutting wirings by occurrence of leakage current and no deterioration of insulation resistance property between the abutting wirings are achieved in case that fine metal wiring is formed in a porous insulation film. The insulation barrier layer 413 is formed between an interlayer insulation film and the metal wiring, in the metal wiring structure on the substrate forming the semiconductor element. The insulation barrier layer enables to reduce leakage current between the abutting wirings and to elevate the insulation credibility.Type: ApplicationFiled: March 1, 2010Publication date: June 17, 2010Applicants: NEC CORPORATION, NEC ELECTRONICS CORPORATIONInventors: Munehiro TADA, Yoshihiro HAYASHI, Yoshimichi HARADA, Fuminori ITO, Hiroto OHTAKE, Tatsuya USAMI