Patents by Inventor Fuminori Ito

Fuminori Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190249716
    Abstract: Raw material powder containing metal powder as a main component is molded to form a metal powder molded body (3?), and the metal powder molded body (3?) is sintered to form a metal substrate (3). Further, a lubricating member (4) is made of an aggregate of graphite particles (13), and at least a part of a bearing surface (11) is formed of the lubricating member (4). The lubricating member (4) is fitted into the metal powder molded body (3?). After that, the metal powder molded body (3?) is sintered, and at this time, the lubricating member (4) is fixed onto the metal substrate (3) with a contraction force (F) generated in the metal powder molded body (3?).
    Type: Application
    Filed: April 25, 2019
    Publication date: August 15, 2019
    Applicant: NTN CORPORATION
    Inventors: Yoshinori ITO, Takahiro GOTOU, Fuminori SATOJI
  • Patent number: 10323689
    Abstract: Raw material powder containing metal powder as a main component is molded to form a metal powder molded body (3?), and the metal powder molded body (3?) is sintered to form a metal substrate (3). Further, a lubricating member (4) is made of an aggregate of graphite particles (13), and at least a part of a bearing surface (11) is formed of the fabricating member (4). The lubricating member (4) is fitted into the metal powder molded body (3?). After that, the metal powder molded body (3?) is sintered, and at this time, the lubricating member (4) is fixed onto the metal substrate (3) with a contraction force (F) generated in the metal powder molded body (3?).
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: June 18, 2019
    Assignee: NTN CORPORATION
    Inventors: Yoshinori Ito, Takahiro Gotou, Fuminori Satoji
  • Publication number: 20190179160
    Abstract: An aerial image display device includes a display component, an imaging component, and a first limiter. The display component has a display surface for displaying an image. The imaging component has a first reflecting surface and a second reflecting surface that are arranged perpendicular to each other along an image formation plane of the imaging component. The imaging component forms an aerial image of the image in a display area that is symmetrical with the display surface with respect to the image formation plane. The first limiter is disposed closer to the display component than the imaging component. The first limiter limits an incident angle of incident light incident on the imaging component. The first reflection surface and the second reflection surface are inclined by an angle between 30° and 60° with respect to a median plane that includes a perpendicular of each of the display surface and the image formation plane.
    Type: Application
    Filed: October 30, 2018
    Publication date: June 13, 2019
    Inventors: Tatsuya Ito, Fuminori Tanaka
  • Patent number: 9236430
    Abstract: The deposition rate of a porous insulation film is increased, and the film strength of the porous insulation film is improved. Two or more organic siloxane raw materials each having a cyclic SiO structure as a main skeleton thereof, and having mutually different structures, are vaporized, and transported with a carrier gas to a reactor (chamber), and an oxidant gas including an oxygen atom is added thereto. Thus, a porous insulation film is formed by a plasma CVD (Chemical Vapor Deposition) method or a plasma polymerization method in the reactor (chamber). In the step, the ratio of the flow rate of the added oxidant gas to the flow rate of the carrier gas is more than 0 and 0.08 or less.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: January 12, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hironori Yamamoto, Fuminori Ito, Yoshihiro Hayashi
  • Publication number: 20150236091
    Abstract: The deposition rate of a porous insulation film is increased, and the film strength of the porous insulation film is improved. Two or more organic siloxane raw materials each having a cyclic SiO structure as a main skeleton thereof, and having mutually different structures, are vaporized, and transported with a carrier gas to a reactor (chamber), and an oxidant gas including an oxygen atom is added thereto. Thus, a porous insulation film is formed by a plasma CVD (Chemical Vapor Deposition) method or a plasma polymerization method in the reactor (chamber). In the step, the ratio of the flow rate of the added oxidant gas to the flow rate of the carrier gas is more than 0 and 0.08 or less.
    Type: Application
    Filed: May 1, 2015
    Publication date: August 20, 2015
    Inventors: Hironori YAMAMOTO, Fuminori ITO, Yoshihiro HAYASHI
  • Patent number: 9034740
    Abstract: The deposition rate of a porous insulation film is increased, and the film strength of the porous insulation film is improved. Two or more organic siloxane raw materials each having a cyclic SiO structure as a main skeleton thereof, and having mutually different structures, are vaporized, and transported with a carrier gas to a reactor (chamber), and an oxidant gas including an oxygen atom is added thereto. Thus, a porous insulation film is formed by a plasma CVD (Chemical Vapor Deposition) method or a plasma polymerization method in the reactor (chamber). In the step, the ratio of the flow rate of the added oxidant gas to the flow rate of the carrier gas is more than 0 and 0.08 or less.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: May 19, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hironori Yamamoto, Fuminori Ito, Yoshihiro Hayashi
  • Patent number: 8937023
    Abstract: A method includes forming an insulating film over a substrate by introducing a cyclic siloxane compound having a cyclic siloxane as a skeleton and having at least one volatile hydrocarbon group bonded to a side chain, and a silicon-containing compound into a plasma, and converting the insulating film to a porous insulating film by adding energy to the insulating film. The silicon-containing compound is decomposed using less energy as compared with the skeleton of the cyclic siloxane compound, the volatile hydrocarbon group, and the bond between the cyclic siloxane compound and the volatile hydrocarbon group.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: January 20, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Fuminori Ito, Yoshihiro Hayashi
  • Patent number: 8790785
    Abstract: A method of forming a porous insulation film uses an organic silica material gas having a 3-membered SiO cyclic structure and a 4-membered SiO cyclic structure, or an organic silica material gas having a 3-membered SiO cyclic structure and a straight-chain organic silica structure, and uses a plasma reaction in the filming process. A porous interlevel dielectric film having a higher strength and a higher adhesive property can be obtained.
    Type: Grant
    Filed: July 23, 2007
    Date of Patent: July 29, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hironori Yamamoto, Fuminori Ito, Munehiro Tada, Yoshihiro Hayashi
  • Patent number: 8598706
    Abstract: A method for forming an interlayer dielectric film by a plasma CVD method, including turning off a radio frequency power and purging with an inert gas simultaneously.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: December 3, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hironori Yamamoto, Fuminori Ito, Yoshihiro Hayashi
  • Patent number: 8592303
    Abstract: There are provided with a wiring structure and a method for manufacturing the same wherein in a wiring structure of multi-layered wiring in which a metal wiring is formed on a substrate forming a semiconductor element thereby obtaining connection of the element, no damage to insulation property between the abutting wirings by occurrence of leakage current and no deterioration of insulation resistance property between the abutting wirings are achieved in case that fine metal wiring is formed in a porous insulation film. The insulation barrier layer 413 is formed between an interlayer insulation film and the metal wiring, in the metal wiring structure on the substrate forming the semiconductor element. The insulation barrier layer enables to reduce leakage current between the abutting wirings and to elevate the insulation credibility.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: November 26, 2013
    Assignees: Renesas Electronics Corporation, NEC Corporation
    Inventors: Munehiro Tada, Yoshihiro Hayashi, Yoshimichi Harada, Fuminori Ito, Hiroto Ohtake, Tatsuya Usami
  • Patent number: 8592283
    Abstract: A semiconductor device manufacturing method for manufacturing a semiconductor device having a transistor mounted in a wiring of a plural-layer structure includes in manufacturing the semiconductor device that is formed on a semiconductor element and includes a barrier insulating film, a porous interlayer insulating film, a wiring, a via plug formed by embedding a metal wiring material in a wiring trench, and a via hole formed in the porous interlayer insulating film, irradiating an electron beam or an ultraviolet ray onto at least a portion of the porous interlayer insulating film before forming an opening in the barrier insulating film.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: November 26, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Fuminori Ito, Yoshihiro Hayashi, Tsuneo Takeuchi
  • Publication number: 20130299952
    Abstract: The deposition rate of a porous insulation film is increased, and the film strength of the porous insulation film is improved. Two or more organic siloxane raw materials each having a cyclic SiO structure as a main skeleton thereof, and having mutually different structures, are vaporized, and transported with a carrier gas to a reactor (chamber), and an oxidant gas including an oxygen atom is added thereto. Thus, a porous insulation film is formed by a plasma CVD (Chemical Vapor Deposition) method or a plasma polymerization method in the reactor (chamber). In the step, the ratio of the flow rate of the added oxidant gas to the flow rate of the carrier gas is more than 0 and 0.08 or less.
    Type: Application
    Filed: May 6, 2013
    Publication date: November 14, 2013
    Applicant: Renesas Electronics Corporation
    Inventors: Hironori YAMAMOTO, Fuminori ITO, Yoshihiro HAYASHI
  • Patent number: 8377823
    Abstract: A method of forming a semiconductor device includes forming a trench on a porous insulating film, placing a chemical material including a structure comprising —Si—O— including vinyl group on a surface of the porous insulating film or in the porous insulating film, and performing polymerization of the chemical material to provide a dielectric film having a density higher than that of porous insulating film on the surface of the trench. The structure may be a structure defined by a formula 1.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: February 19, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Masayoshi Tagami, Fuminori Ito
  • Patent number: 8278763
    Abstract: The present invention provides a multilayer wiring technology by which high adhesiveness and high insulation reliability between wirings are obtained, while maintaining effective low capacitance between wirings. A semiconductor device is characterized in that a first insulating film is an insulating film formed of at least one layer which contains a siloxane structure containing silicon, oxygen and carbon; the siloxane structure in the inner part of the first insulating film contains a larger number of carbon atoms than the number of silicon atoms; and a modified layer which containing a smaller number of carbon atoms and a larger number of oxygen atoms per unit volume than the inner part of the first insulating film is formed on at least one of an interface between the first insulating film and the metal and an interface between the first insulating film and a second insulating film.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: October 2, 2012
    Assignee: NEC Corporation
    Inventors: Munehiro Tada, Hiroto Ohtake, Fuminori Ito, Yoshihiro Hayashi, Hironori Yamamoto
  • Publication number: 20120135611
    Abstract: A method includes forming an insulating film over a substrate by introducing a cyclic siloxane compound having a cyclic siloxane as a skeleton and having at least one volatile hydrocarbon group bonded to a side chain, and a silicon-containing compound into a plasma, and converting the insulating film to a porous insulating film by adding energy to the insulating film. The silicon-containing compound is decomposed using less energy as compared with the skeleton of the cyclic siloxane compound, the volatile hydrocarbon group, and the bond between the cyclic siloxane compound and the volatile hydrocarbon group.
    Type: Application
    Filed: February 1, 2012
    Publication date: May 31, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Fuminori ITO, Yoshihiro HAYASHI
  • Patent number: 8133821
    Abstract: A method includes forming an insulating film over a substrate by introducing a cyclic siloxane compound having a cyclic siloxane as a skeleton and having at least one volatile hydrocarbon group bonded to a side chain, and a silicon-containing compound into a plasma, and converting the insulating film to a porous insulating film by adding energy to the insulating film. The silicon-containing compound is decomposed using less energy as compared with the skeleton of the cyclic siloxane compound, the volatile hydrocarbon group, and the bond between the cyclic siloxane compound and the volatile hydrocarbon group.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: March 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Fuminori Ito, Yoshihiro Hayashi
  • Publication number: 20120013023
    Abstract: The present invention provides a multilayer wiring technology by which high adhesiveness and high insulation reliability between wirings are obtained, while maintaining effective low capacitance between wirings. A semiconductor device is characterized in that a first insulating film is an insulating film formed of at least one layer which contains a siloxane structure containing silicon, oxygen and carbon; the siloxane structure in the inner part of the first insulating film contains a larger number of carbon atoms than the number of silicon atoms; and a modified layer which containing a smaller number of carbon atoms and a larger number of oxygen atoms per unit volume than the inner part of the first insulating film is formed on at least one of an interface between the first insulating film and the metal and an interface between the first insulating film and a second insulating film.
    Type: Application
    Filed: September 21, 2011
    Publication date: January 19, 2012
    Applicant: NEC CORPORATION
    Inventors: Munehiro TADA, Hiroto OHTAKE, Fuminori ITO, Yoshihiro HAYASHI, Hironori YAMAMOTO
  • Publication number: 20110318926
    Abstract: A semiconductor device manufacturing method for manufacturing a semiconductor device having a transistor mounted in a wiring of a plural-layer structure includes in manufacturing the semiconductor device that is formed on a semiconductor element and includes a barrier insulating film, a porous interlayer insulating film, a wiring, a via plug formed by embedding a metal wiring material in a wiring trench, and a via hole formed in the porous interlayer insulating film, irradiating an electron beam or an ultraviolet ray onto at least a portion of the porous interlayer insulating film before forming an opening in the barrier insulating film.
    Type: Application
    Filed: August 30, 2011
    Publication date: December 29, 2011
    Applicant: NEC CORPORATION
    Inventors: Fuminori Ito, Yoshihiro Hayashi, Tsuneo Takeuchi
  • Patent number: 8043957
    Abstract: The present invention provides a multilayer wiring technology by which high adhesiveness and high insulation reliability between wirings are obtained, while maintaining effective low capacitance between wirings. A semiconductor device is characterized in that a first insulating film is an insulating film formed of at least one layer which contains a siloxane structure containing silicon, oxygen and carbon; the siloxane structure in the inner part of the first insulating film contains a larger number of carbon atoms than the number of silicon atoms; and a modified layer which containing a smaller number of carbon atoms and a larger number of oxygen atoms per unit volume than the inner part of the first insulating film is formed on at least one of an interface between the first insulating film and the metal and an interface between the first insulating film and a second insulating film.
    Type: Grant
    Filed: May 16, 2007
    Date of Patent: October 25, 2011
    Assignee: NEC Corporation
    Inventors: Munehiro Tada, Hiroto Ohtake, Fuminori Ito, Yoshihiro Hayashi, Hironori Yamamoto
  • Patent number: 8039921
    Abstract: A semiconductor device with a high-strength porous modified layer having a pore size of 1 nm or less, which is formed, in a multilayer wiring forming process, by forming a via hole and a wiring trench in a via interlayer insulating film and a wiring interlayer insulting film and then irradiating an electron beam or an ultraviolet ray onto the opening side walls.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: October 18, 2011
    Assignee: NEC Corporation
    Inventors: Fuminori Ito, Yoshihiro Hayashi, Tsuneo Takeuchi