Patents by Inventor Fuminori Ito

Fuminori Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100123223
    Abstract: A method includes forming an insulating film over a substrate by introducing a cyclic siloxane compound having a cyclic siloxane as a skeleton and having at least one volatile hydrocarbon group bonded to a side chain, and a silicon-containing compound into a plasma, and converting the insulating film to a porous insulating film by adding energy to the insulating film. The silicon-containing compound is decomposed using less energy as compared with the skeleton of the cyclic siloxane compound, the volatile hydrocarbon group, and the bond between the cyclic siloxane compound and the volatile hydrocarbon group.
    Type: Application
    Filed: November 18, 2009
    Publication date: May 20, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Fuminori ITO, Yoshihiro HAYASHI
  • Patent number: 7701060
    Abstract: There are provided with a wiring structure and a method for manufacturing the same wherein in a wiring structure of multi-layered wiring in which a metal wiring is formed on a substrate forming a semiconductor element thereby obtaining connection of the element, no damage to insulation property between the abutting wirings by occurrence of leakage current and no deterioration of insulation resistance property between the abutting wirings are achieved in case that fine metal wiring is formed in a porous insulation film. The insulation barrier layer 413 is formed between an interlayer insulation film and the metal wiring, in the metal wiring structure on the substrate forming the semiconductor element. The insulation barrier layer enables to reduce leakage current between the abutting wirings and to elevate the insulation credibility.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: April 20, 2010
    Assignees: NEC Corporation, NEC Electronics Corporation
    Inventors: Munehiro Tada, Yoshihiro Hayashi, Yoshimichi Harada, Fuminori Ito, Hiroto Ohtake, Tatsuya Usami
  • Publication number: 20100025852
    Abstract: To suppress deterioration in reliability of wiring and to reduce effective dielectric constant of wiring. In a semiconductor device, copper-containing wirings are covered by barrier insulating films, and the barrier insulating films contain a component of an organic silica containing unsaturated hydrocarbon and amorphous carbon. The copper-containing wirings are covered by the barrier insulating films that contain a component that is in an organic silica structure containing unsaturated hydrocarbon and amorphous carbon. Accordingly, inter-wiring capacitance is reduced without deteriorating reliability of the copper-containing wiring, thereby realizing a high-speed LSI with low power consumption.
    Type: Application
    Filed: December 20, 2007
    Publication date: February 4, 2010
    Inventors: Makoto Ueki, Hironori Yamamoto, Yoshihiro Hayashi, Fuminori Ito, Yoshiyuki Fukumoto
  • Publication number: 20090267198
    Abstract: The present invention provides a multilayer wiring technology by which high adhesiveness and high insulation reliability between wirings are obtained, while maintaining effective low capacitance between wirings. A semiconductor device is characterized in that a first insulating film is an insulating film formed of at least one layer which contains a siloxane structure containing silicon, oxygen and carbon; the siloxane structure in the inner part of the first insulating film contains a larger number of carbon atoms than the number of silicon atoms; and a modified layer which containing a smaller number of carbon atoms and a larger number of oxygen atoms per unit volume than the inner part of the first insulating film is formed on at least one of an interface between the first insulating film and the metal and an interface between the first insulating film and a second insulating film.
    Type: Application
    Filed: May 16, 2007
    Publication date: October 29, 2009
    Applicant: NEC CORPORATION
    Inventors: Munehiro Tada, Hiroto Ohtake, Fuminori Ito, Yoshihiro Hayashi, Hironori Yamamoto
  • Publication number: 20090246538
    Abstract: A method of forming a porous insulation film uses an organic silica material gas having a 3-membered SiO cyclic structure and a 4-membered SiO cyclic structure, or an organic silica material gas having a 3-membered SiO cyclic structure and a straight-chain organic silica structure, and uses a plasma reaction in the filming process. A porous interlevel dielectric film having a higher strength and a higher adhesive property can be obtained.
    Type: Application
    Filed: July 23, 2007
    Publication date: October 1, 2009
    Inventors: Hironori Yamamoto, Fuminori Ito, Munehiro Tada, Yoshihiro Hayashi
  • Publication number: 20090127669
    Abstract: A method for forming an interlayer dielectric film by a plasma CVD method, including turning off a radio frequency power and purging with an inert gas simultaneously.
    Type: Application
    Filed: September 17, 2008
    Publication date: May 21, 2009
    Applicant: NEC Corporation
    Inventors: Hironori YAMAMOTO, Fuminori ITO, Yoshihiro HAYASHI
  • Publication number: 20090072403
    Abstract: A semiconductor device with a high-strength porous modified layer having a pore size of 1 nm or less, which is formed, in a multilayer wiring forming process, by forming a via hole and a wiring trench in a via interlayer insulating film and a wiring interlayer insulting film and then irradiating an electron beam or an ultraviolet ray onto the opening side walls.
    Type: Application
    Filed: September 15, 2006
    Publication date: March 19, 2009
    Inventors: Fuminori Ito, Yoshihiro Hayashi, Tsuneo Takeuchi
  • Patent number: 7264978
    Abstract: A field emission type cold cathode, comprising a substrate having a conductivity at least on the surface thereof, an insulation layer formed on the substate and having a first opening part, a gate electrode layer formed on the insulation layer, having a center generally aligned with the center of the first opening part, and having, therein, a second opening part having an opening diameter larger than the opening diameter of the first opening part, and an emitter layer formed in the first opening part, the emitter layer characterized by further comprising the bottom surface and the side surfaces of the first opening part.
    Type: Grant
    Filed: June 18, 2002
    Date of Patent: September 4, 2007
    Assignee: NEC Corporation
    Inventor: Fuminori Ito
  • Publication number: 20070013069
    Abstract: A multilayer wiring structure for connecting a semiconductor device is disclosed which is obtained by forming metal wirings on a substrate in which the semiconductor device is formed. The wiring structure free from such conventional problems that insulation between wirings next to each other is damaged or insulation resistance between wirings next to each other is deteriorated by generation of leakage current when fine metal wirings are formed in a porous insulating film. A method for producing such a wiring structure is also disclosed. In the metal wiring structure on the substrate in which the semiconductor device is formed, a insulating barrier layer (413) containing an organic matter is formed between an interlayer insulating film and a metal wiring. This insulating barrier layer reduces leakage current between wirings next to each other, thereby improving insulation reliability.
    Type: Application
    Filed: May 28, 2004
    Publication date: January 18, 2007
    Inventors: Munehiro Tada, Yoshihiro Hayashi, Yoshimichi Harada, Fuminori Ito, Hiroto Ohtake, Tatsuya Usami
  • Patent number: 7161285
    Abstract: A fabrication method for an emitter includes the steps of forming on a glass substrate a CNT film which contains a plurality of carbon nanotubes (CNTs) and constitutes an emitter electrode, forming a gate electrode via an insulating film on the CNT film, forming a plurality of gate openings in the gate electrode and the insulating film, and aligning upright the CNTs in the gate opening. The upright alignment generates a stable uniform emission current and provides excellent emission characteristics.
    Type: Grant
    Filed: November 19, 2001
    Date of Patent: January 9, 2007
    Assignee: NEC Corporation
    Inventors: Akihiko Okamoto, Kazuo Konuma, Yoshinori Tomihari, Fuminori Ito, Yuko Okada
  • Publication number: 20040174110
    Abstract: A field emission type cold cathode, comprising a substrate having a conductivity at least on the surface thereof, an insulation layer formed on the substate and having a first opening part, a gate electrode layer formed on the insulation layer, having a center generally aligned with the center of the first opening part, and having, therein, a second opening part having an opening diameter larger than the opening diameter of the first opening part, and an emitter layer formed in the first opening part, the emitter layer characterized by further comprising the bottom surface and the side surfaces of the first opening part.
    Type: Application
    Filed: December 18, 2003
    Publication date: September 9, 2004
    Inventor: Fuminori Ito
  • Publication number: 20040104660
    Abstract: A fabrication method for an emitter includes the steps of forming on a glass substrate (10) a CNT film (12) which contains a plurality of carbon nanotubes (CNTs) (12a) and constitutes an emitter electrode (12b), forming a gate electrode (16) via an insulating film (13) on the CNT film (12), forming a plurality of gate openings (17) in the gate electrode (16) and the insulating film (13), and aligning upright the CNTs (12a) in the gate opening (17). The upright alignment generates a stable uniform emission current and provides excellent emission characteristics.
    Type: Application
    Filed: December 22, 2003
    Publication date: June 3, 2004
    Inventors: Akihiko Okamoto, Kazuo Konuma, Yoshinori Tomihari, Fuminori Ito, Yuko Okada
  • Publication number: 20040043219
    Abstract: Upon wet etching and thereby patterning carbon nanotubes (106) by a transfer method, a solution for dissolving a binder used in the transfer method as a solution used for the wet etching is used, and the carbon nanotubes (106) tangled with each other are rubbed off with a cloth-like substance (112) upon the wet etching. Furthermore, upon patterning the carbon nanotubes (106) using a dry etching method, a metal film or a film made of a substance resistant to damage upon the dry etching and causing no damage to the carbon nanotubes (106) when removed is used as a mask. A fine carbon nanotube pattern having an excellent flatness is formed.
    Type: Application
    Filed: May 29, 2003
    Publication date: March 4, 2004
    Inventors: Fuminori Ito, Yuko Okada, Yoshinori Tomihari, Kazuo Konuma, Akihiko Okamoto
  • Publication number: 20030080663
    Abstract: A field emission type cold cathode, a flat display and a method for a same are provided which are capable of improving controllability in formation of an emitter and of generating uniform and stable emission current. The emitter composed of a carbon nano-tube having a length being not more than, at least, a film thickness of an insulating layer is formed on a glass substrate on which a conductive layer is formed.
    Type: Application
    Filed: December 5, 2002
    Publication date: May 1, 2003
    Applicant: NEC CORPORATION
    Inventor: Fuminori Ito
  • Publication number: 20020009943
    Abstract: An insulating layer 2 and a gate electrode layer 1 are sequentially formed on a conductive substrate 3; then the insulating layer 3 and the gate electrode layer 1 are etched to form an opening extending to the conductive substrate 3; then an emitter material is deposited on the surfaces of the conductive substrate 3 and of the gate electrode layer 1 which are exposed on the bottom of the said opening from a direction vertical to the conductive substrate 3, to form a sharp emitter tip 5 within the opening; and finally the emitter material deposited on the upper face of the gate electrode layer 1 is removed, to provide a field emission cathode.
    Type: Application
    Filed: November 30, 1998
    Publication date: January 24, 2002
    Inventor: FUMINORI ITO
  • Patent number: 6340425
    Abstract: In the manufacturing of the cold cathode device which has a porous silicon portion as an emitter portion, the silicon layer is given an electric potential, while the gate electrode is given an electric potential lower than that of the silicon layer. And thereby, the predetermined portion of the silicon layer is subjected to anodic etching to be rendered into the porous silicon portion. With such anodic etching, the cold cathode device with the porous silicon portion is obtained.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: January 22, 2002
    Assignee: NEC Corporation
    Inventor: Fuminori Ito
  • Publication number: 20010052469
    Abstract: In the manufacturing of the cold cathode device which has a porous silicon portion as an emitter portion, the silicon layer is given an electric potential, while the gate electrode is given an electric potential lower than that of the silicon layer. And thereby, the predetermined portion of the silicon layer is subjected to anodic etching to be rendered into the porous silicon portion. With such anodic etching, the cold cathode device with the porous silicon portion is obtained.
    Type: Application
    Filed: April 7, 2000
    Publication date: December 20, 2001
    Inventor: Fuminori Ito
  • Patent number: 6236156
    Abstract: The present invention provides a micro vacuum pump capable of enhancing the performance of exhausting rare gases as well as active gases thereby to ensure quality, good repeatability and stable getter action of the micro vacuum pump over a long time. The invention also provides an apparatus assembling the micro vacuum pump. The micro vacuum pump capable of maintaining a high degree of vacuum includes a first conductive substrate having many protrusions and mounting a second conductive substrate disposed with a predetermined interval provided with respect to the first conductive substrate so that it faces the protrusions. A gate electrode is disposed in the vicinity of the apexes of the protrusions on the first conductive substrate via an insulator layer, and is positioned to face the second conductive substrate.
    Type: Grant
    Filed: August 6, 1998
    Date of Patent: May 22, 2001
    Assignee: NEC Corporation
    Inventor: Fuminori Ito
  • Patent number: 6114694
    Abstract: The present invention discloses a field emission type cold cathode incorporated device, which comprises a field emission type cold cathode having a number of electron emitting sections, said sections having sharp projections, and a vacuum tank for placing the field emission type cold cathode in a vacuum environment. In this device, a partial pressure of particular noble gas in residual gas contained in the vacuum tank is set equal to or lower than C/I (C is a constant and I is a maximum emission current value per one of the number of electron emitting sections during driving of the field emission type cold cathode). Also, in order to set a partial pressure of the particular noble gas in the residual gas contained in the vacuum tank equal to C/I (C: constant) or lower, a partial pressure of the particular residual gas in the vacuum tank is monitored by a mass analyzer during vacuum tank exhaustion.
    Type: Grant
    Filed: March 23, 1998
    Date of Patent: September 5, 2000
    Assignee: NEC Corporation
    Inventor: Fuminori Ito
  • Patent number: 6040973
    Abstract: A field emission cold cathode device is driven to make an emission current constant without limiting the available choice of materials for a gate electrode. A positive voltage with reference to OV is applied from a gate power supply to gate electrode of the field emission cold cathode device to enable emitter disposed respectively near the gate electrode to emit electrons. After the positive voltage with reference to OV is applied, a negative voltage with reference to OV is applied from the gate power supply to the gate electrode at a predetermined time.
    Type: Grant
    Filed: January 28, 1998
    Date of Patent: March 21, 2000
    Assignee: NEC Corporaiton
    Inventors: Akihiko Okamoto, Fuminori Ito