Abstract: A memory system of an embodiment includes a memory, a controller configured to control the memory, and a first board on which the memory and the controller are mounted. The memory system further includes a module component including at least one capacitor, a second board, and a wiring member, each of the at least one capacitor including a lead, the at least one capacitor being mounted on the second board, the wiring member being electrically connected to the lead of the at least one capacitor and extending from the second board. The first board and the module component are connected to each other via the wiring member.

Abstract: According to one embodiment, a memory system includes: a first package including a first memory chip configured to store data, and a first chip containing a first circuit configured to control an On Die Termination (ODT) operation based on a first signal which is a control signal for reading of data stored in the first memory chip; a second package including a second memory chip configured to store data, and a second chip containing a second circuit configured to control the ODT operation based on the first signal, the first signal also being a control signal for reading of data stored in the second memory chip; and a controller configured to transmit the first signal to the first chip and the second chip.

Abstract: A memory system includes a first substrate including a first signal terminal and a second signal terminal electrically connected to a bus, a first circuit in which a first switching element and a first resistor are connected in series between a first terminal and a second terminal, the first terminal connected to the first signal terminal, a second circuit in which a second switching element and a second resistor are connected in series between a third terminal and a fourth terminal, the third terminal connected to the second signal terminal, a first memory electrically connected to the second terminal, a second memory electrically connected to the fourth terminal, and a controller electrically connected to the bus and configured to control the first and second switching elements.

Abstract: A memory system includes a first substrate including a first signal terminal and a second signal terminal electrically connected to a bus, a first circuit in which a first switching element and a first resistor are connected in series between a first terminal and a second terminal, the first terminal connected to the first signal terminal, a second circuit in which a second switching element and a second resistor are connected in series between a third terminal and a fourth terminal, the third terminal connected to the second signal terminal, a first memory electrically connected to the second terminal, a second memory electrically connected to the fourth terminal, and a controller electrically connected to the bus and configured to control the first and second switching elements.

Abstract: A semiconductor memory device includes a semiconductor memory unit, a memory controller, a cover unit having a first portion covering the semiconductor memory unit and a second portion covering the memory controller, a first heat conduction member disposed between the semiconductor memory unit and the first portion of the cover unit, and a second heat conduction member disposed between the memory controller and the second portion of the cover. The cover unit has a gap formed between the first and second portions.

Abstract: According to one embodiment, there is provided a memory system including a 1st memory group, a 2nd memory group, a power supply voltage adjustment circuit, a 1st line, a 1st switch, a 2nd line, a 3rd line, and a 4th line. The power supply voltage adjustment circuit includes a 1st terminal and a 2nd terminal. The 1st line electrically connects the 1st terminal to the 1st memory group. The 1st switch includes a 3rd terminal, a 4th terminal, and a 5th terminal. The 1st switch electrically connects the 3rd terminal to the 4th terminal when turned on. The 2nd line electrically connects the 1st terminal to the 3rd terminal. The 3rd line electrically connects the 4th terminal to the 2nd memory group. The 4th line electrically connects the 2nd terminal to the 5th terminal.

Abstract: A semiconductor memory device includes a semiconductor memory unit, a memory controller, a cover unit having a first portion covering the semiconductor memory unit and a second portion covering the memory controller, a first heat conduction member disposed between the semiconductor memory unit and the first portion of the cover unit, and a second heat conduction member disposed between the memory controller and the second portion of the cover. The cover unit has a gap formed between the first and second portions.

Abstract: According to one embodiment, a semiconductor memory device includes: a first component including a controller which issues an instruction complying with a NAND interface; and a second component including a first NAND flash memory which is controlled by the instruction, the second component being removable from the first component.

Abstract: A composition for lowering a blood uric acid level is characterized by comprising taurine as an active ingredient.

Abstract: In a curtain shield airbag mounting structure for mounting a curtain shield airbag to a side upper portion of a vehicle body, the curtain shield airbag includes an airbag main body and a resin case which holds the airbag main body. A base end portion of a folded-back portion of the airbag main body is disposed to oppose a boundary portion between a rear pillar garnish and a ceiling member, or in the vicinity thereof. A guide wall portion is provided at a rear end portion of the resin guide case. The guide wall portion opposes a rear end side of a base end portion of the folded-back portion and prevents the folded-back portion from colliding with the rear pillar garnish when the folded-back portion opens while pushing out a part of the ceiling member.

Abstract: In a curtain shield airbag mounting structure for mounting a curtain shield airbag to a side upper portion of a vehicle body, the curtain shield airbag includes an airbag main body and a resin case which holds the airbag main body. A base end portion of a folded-back portion of the airbag main body is disposed to oppose a boundary portion between a rear pillar garnish and a ceiling member, or in the vicinity thereof. A guide wall portion is provided at a rear end portion of the resin guide case. The guide wall portion opposes a rear end side of a base end portion of the folded-back portion and prevents the folded-back portion from colliding with the rear pillar garnish when the folded-back portion opens while pushing out a part of the ceiling member.

Abstract: A composition for lowering a blood uric acid level is characterized by comprising taurine as an active ingredient.

Abstract: In a network where a plurality of large-scale network address translation (LSN) devices are disposed, a relay apparatus acquires the numbers of sessions held by the plurality of LSN devices in the network and allocates a packet received from a subscriber to the LSN device holding the smallest number of sessions or to the LSN device having a fewer number of sessions than a predetermined threshold, thereby distributing subscriber sessions evenly to the plurality of LSN devices.

Abstract: In an LAC device, if switching occurs to an active system of redundant control section, the failover is implemented by learning Ns (sequence number) and Nr (receive acknowledgement response number) included in a control message received from an LNS device after switching, and sending a ZLB-ACK message using this Ns and Nr.

Abstract: A separator for an electric double layer capacitor, characterized in that a thickness of the entire separator is 25 ?m or less, a layer of an ultrafine fibrous aggregate prepared by an electrostatic spinning process is contained, an average fiber diameter of ultrafine fibers constituting the ultrafine fibrous aggregate layer is 1 ?m or less, and a maximum pore size of the ultrafine fibrous aggregate is not more than 3 times a mean flow pore size is disclosed.

Abstract: A separator for an electric double layer capacitor, characterized in that a thickness of the entire separator is 25 ?m or less, a layer of an ultrafine fibrous aggregate prepared by an electrostatic spinning process is contained, an average fiber diameter of ultrafine fibers constituting the ultrafine fibrous aggregate layer is 1 ?m or less, and a maximum pore size of the ultrafine fibrous aggregate is not more than 3 times a mean flow pore size is disclosed.

Abstract: A process for manufacturing an electric double-layer capacitor with an excellent property of preventing a short circuit between the electrodes, a better ionic permeability and a high strength is provided, said process comprising using, as a separator, a fiber sheet containing a fiber having fibrils and a fine polyester fiber having a fineness of not more than 0.45 dtex (decitex) and drying the separator at a specific temperature.

Abstract: A separator for an electric double-layer capacitor with an excellent property of preventing a short circuit between the electrodes, a good ionic permeability and a high strength is provided by a fiber sheet including a fibril-containing fiber and a fine polyester fiber having a fineness of not more than 0.45 dtex (decitex).

Abstract: There is provided a composition for external use with a reduced skin irritation comprising minoxidil and 0.01 to 2 parts by weight of at least one antihistaminic agent selected from the group consisting of chlorphenylamine maleate, diphenylimidazole, diphenhydramine and a salt thereof per 1 part by weight of minoxidil.

Abstract: A separator for an electric double-layer capacitor with an excellent property of preventing a short circuit between the electrodes, a good ionic permeability and a high strength is provided which comprises a fiber sheet comprising a fibril-containing fiber and a fine polyester fiber having a fineness of not more than 0.45 dtex (decitex).