Patents by Inventor Fumio Inoue

Fumio Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130292464
    Abstract: An analyzer which analyzes an analyte by using the analyte and consumables, the analyzer comprising: an automatic reading device which reads a first product information related to a consumable via an identifier given to the consumable or a container containing the consumable; and a controller which permits an analysis operation when the first product information is suitable information read by the automatic reading device via the identifier, and prompts an operator to manually enter a second product information comprising information specifying the manufacturer or seller of the consumable when the automatic reading device cannot read the identifier or the information read via the identifier is not suitable as the first product information and permits the analysis operation and storage of the input second product information when the operator has entered the second product information.
    Type: Application
    Filed: June 6, 2013
    Publication date: November 7, 2013
    Inventors: Toru MIZUMOTO, Fumio INOUE
  • Patent number: 8474692
    Abstract: An analyzer which analyzes an analyte by using the analyte and consumables, the analyzer comprising: an automatic reading device which reads a first product information related to a consumable via an identifier given to the consumable or a container containing the consumable; and a controller which permits an analysis operation when the first product information is suitable information read by the automatic reading device via the identifier, and prompts an operator to manually enter a second product information comprising information specifying the manufacturer or seller of the consumable when the automatic reading device cannot read the identifier or the information read via the identifier is not suitable as the first product information and permits the analysis operation and storage of the input second product information when the operator has entered the second product information.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: July 2, 2013
    Assignee: Sysmex Corporation
    Inventors: Toru Mizumoto, Fumio Inoue
  • Publication number: 20120074214
    Abstract: An analyzer which analyzes an analyte by using the analyte and consumables, the analyzer comprising: an automatic reading device which reads a first product information related to a consumable via an identifier given to the consumable or a container containing the consumable; and a controller which permits an analysis operation when the first product information is suitable information read by the automatic reading device via the identifier, and prompts an operator to manually enter a second product information comprising information specifying the manufacturer or seller of the consumable when the automatic reading device cannot read the identifier or the information read via the identifier is not suitable as the first product information and permits the analysis operation and storage of the input second product information when the operator has entered the second product information.
    Type: Application
    Filed: September 28, 2011
    Publication date: March 29, 2012
    Inventors: Toru Mizumoto, Fumio Inoue
  • Patent number: 8028402
    Abstract: Disclosed is a manufacturing method of a multi-layer wiring board, which method includes: preparing connection boards, the connection boards having respectively an insulating resin composition layer, a connection conductor formed so as to pass through the insulating resin composition layer and a conductor circuit formed on the insulating resin composition layer and connected to the connection conductor; aligning the connection boards; and laminating the aligned connection boards by heating and pressing, so that the connection conductors, or the connection conductor and the conductor circuit, are conductively connected with each other, and the connection boards are mechanically connected with each other by the insulating resin composition layer. The connection boards are formed by specified processing, including use of a three-layer composite metallic layer.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: October 4, 2011
    Assignee: Hitachi Chemical Co., Ltd.
    Inventors: Hidehiro Nakamura, Akishi Nakaso, Shigeharu Arike, Fumio Inoue, Tetsuya Enomoto, Norio Moriike, Kousuke Hiroki
  • Publication number: 20110147072
    Abstract: An object of the present invention is to provide a copper surface treatment method capable of keeping certainly a bonding strength between a copper surface and a resist, or between a copper surface and an insulating resin without forming irregularities having sizes of more than 1 ?m on the copper surface, and a copper treated with the method. The surface treatment method, comprising: a first step of forming, on a copper surface, a nobler metal than the copper discretely; a second step, subsequent to the first step, of forming copper oxide on the copper surface by oxidation with an alkaline solution containing an oxidizing agent; and third step of dissolving the copper oxide so as to be removed, thereby forming irregularities on the copper surface.
    Type: Application
    Filed: June 17, 2009
    Publication date: June 23, 2011
    Inventors: Tomoaki Yamashita, Sumiko Nakajima, Sadao Itou, Fumio Inoue, Shigeharu Arike
  • Patent number: 7588835
    Abstract: A method of treating the surface of copper is provided to ensure adhesive strength between the surface of copper and an insulating layer without forming irregularities exceeding 1 ?m on the surface of copper and to improve insulation reliability between wirings. A copper whose surface is treated by the above surface treating method is also provided. The method of treating the surface of copper comprises the surface of copper comprising the steps of: forming a metal nobler than copper discretely on the surface of copper; and subsequently oxidizing the surface of copper by using an alkaline solution containing an oxidant.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: September 15, 2009
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Tomoaki Yamashita, Yasuo Inoue, Masaharu Matsuura, Toyoki Ito, Akira Shimizu, Fumio Inoue, Akishi Nakaso
  • Patent number: 7486334
    Abstract: An image display system includes a display device, an input section to which video signals of an interlace scanning system are inputted, a signal converter section which increases horizontal scanning lines of the inputted video signals in number by a factor of at least two, and which generates first and second fields, each of the fields including effective scanning lines used for displaying and ineffective scanning lines not used for displaying, with the effective and ineffective scanning lines being arranged alternately in each of the fields, and a display control section which controls the display device to display the first and second fields alternately. The display control section controls the display device such that positions of the effective scanning lines of the first fields correspond with those of the ineffective scanning lines of the second fields, and vice versa.
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: February 3, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Kouzou Masuda, Ikuya Arai, Sadao Tsuruga, Jiro Kawasaki, Tsuyoshi Sano, Tamotsu Nagabayashi, Ryuuichi Someya, Fumio Inoue, Kouji Kitou, Yasuhiro Imai, Masatoshi Hirose
  • Publication number: 20090008141
    Abstract: The present invention provides a connection board that is formed by an insulating resin composition layer made of one layer or two or more layers and a connection conductor that is formed so as to pass through the insulating resin composition layer in its thickness direction at a position where a conductor circuit is connected, and a multi-layer wiring board, a substrate for semiconductor package and a semiconductor package using the connection board, and methods for manufacturing them.
    Type: Application
    Filed: September 2, 2008
    Publication date: January 8, 2009
    Inventors: Hidehiro Nakamura, Akishi Nakaso, Shigeharu Arike, Fumio Inoue, Tetsuya Enomoto, Norio Moriike, Kousuke Hiroki
  • Publication number: 20080289868
    Abstract: The present invention provides a connection board that is formed by an insulating resin composition layer made of one layer or two or more layers and a connection conductor that is formed so as to pass through the insulating resin composition layer in its thickness direction at a position where a conductor circuit is connected, and a multi-layer wiring board, a substrate for semiconductor package and a semiconductor package using the connection board, and methods for manufacturing them.
    Type: Application
    Filed: July 30, 2008
    Publication date: November 27, 2008
    Inventors: Hidehiro Nakamura, Akishi Nakaso, Shigeharu Arike, Fumio Inoue, Tetsuya Enomoto, Norio Moriike, Kousuke Hiroki
  • Publication number: 20080096046
    Abstract: A method of treating the surface of copper is provided to ensure adhesive strength between the surface of copper and an insulating layer without forming irregularities exceeding 1 ?m on the surface of copper and to improve insulation reliability between wirings. A copper whose surface is treated by the above surface treating method is also provided. The method of treating the surface of copper comprises the surface of copper comprising the steps of: forming a metal nobler than copper discretely on the surface of copper; and subsequently oxidizing the surface of copper by using an alkaline solution containing an oxidant.
    Type: Application
    Filed: March 10, 2006
    Publication date: April 24, 2008
    Inventors: Tomoaki Yamashita, Yasuo Inoue, Masaharu Matsuura, Toyoki Ito, Akira Shimizu, Fumio Inoue, Akishi Nakaso
  • Publication number: 20080010819
    Abstract: The present invention provides a connection board that is formed by an insulating resin composition layer made of one layer or two or more layers and a connection conductor that is formed so as to pass through the insulating resin composition layer in its thickness direction at a position where a conductor circuit is connected, and a multi-layer wiring board, a substrate for semiconductor package and a semiconductor package using the connection board, and methods for manufacturing them.
    Type: Application
    Filed: July 10, 2007
    Publication date: January 17, 2008
    Inventors: Hidehiro NAKAMURA, Akishi Nakaso, Shigeharu Arike, Fumio Inoue, Tetsuya Enomoto, Norio Moriike, Kousuke Hiroki
  • Patent number: 7187072
    Abstract: A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.
    Type: Grant
    Filed: November 10, 2003
    Date of Patent: March 6, 2007
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Naoki Fukutomi, Yoshiaki Tsubomatsu, Fumio Inoue, Toshio Yamazaki, Hirohito Ohhata, Shinsuke Hagiwara, Noriyuki Taguchi, Hiroshi Nomura
  • Publication number: 20060162956
    Abstract: The present invention provides a connection board that is formed by an insulating resin composition layer made of one layer or two or more layers and a connection conductor that is formed so as to pass through the insulating resin composition layer in its thickness direction at a position where a conductor circuit is connected, and a multi-layer wiring board, a substrate for semiconductor package and a semiconductor package using the connection board, and methods for manufacturing them.
    Type: Application
    Filed: December 24, 2002
    Publication date: July 27, 2006
    Inventors: Hidehiro Nakamura, Akishi Nakaso, Shigeharu Arike, Fumio Inoue, Tetsduya Enomoto, Norio Moriike, Kousuke Hiroki
  • Patent number: 7043860
    Abstract: A symbol illuminator of game machines includes a wheel member having symbols at an outer circumferential surface thereof; a casing for the wheel member attached a printed circuit board having a plurality of illuminants; and a reflective frame member having enclosure walls expanding outwardly to a forward direction from a central part thereof, having a plurality of windows into which the illuminants are set, the illuminants being arranged so as to project inside a center part of the reflective frame member; and a projection part, having a reflective face, reflecting the light emitted by the illuminants toward at least the symbol from the inner side of the wheel member so that it can irradiate a reflex of a reflective frame member equally without spots to the symbol of wheel member and can reduce the number of the parts.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: May 16, 2006
    Assignee: Wing Co., Ltd.
    Inventor: Fumio Inoue
  • Patent number: 6917440
    Abstract: A search is conducted through a registered large advertising list to judge whether there are at least two large ad advertisers with credit of at least one in the large ad list. If not, free printing is inhibited. If so, a search is made for small ad advertisers to check if there are at least three small ad advertisers with credit of at least one. If not, free printing is inhibited. If so, free printing is allowed. In this way, an image output system can be provided capable of producing a high image quality print with a sub image added thereto at no charge or a small charge by imposing a certain limit.
    Type: Grant
    Filed: February 5, 2001
    Date of Patent: July 12, 2005
    Assignee: Minolta Co., Ltd.
    Inventors: Shoji Kondo, Fumio Inoue
  • Publication number: 20050001932
    Abstract: An image display system includes a memory for storing at least one scanning line of an inputted video signal of the interlace scanning system, and reading means for repeating to read the video signal of one scanning line from the memory at a speed which is n (n is an integer of 2 or more) times of the writing speed of the video signal for the memory for a horizontal scanning period which is 1/n of the writing period and to stop reading for a horizontal scanning period of the remaining (n?1)/n for each scanning line of one field which is sequentially inputted and reading each scanning line so that the continuous fields interpolate the period of stopping of reading from the memory each other.
    Type: Application
    Filed: July 23, 2004
    Publication date: January 6, 2005
    Inventors: Kouzou Masuda, Ikuya Arai, Sadao Tsuruga, Jiro Kawasaki, Tsuyoshi Sano, Tamotsu Nagabayashi, Ryuuichi Someya, Fumio Inoue, Kouji Kitou, Yasuhiro Imai, Masatoshi Hirose
  • Publication number: 20040200102
    Abstract: A symbol illuminator of game machines includes a wheel member having symbols at an outer circumferential surface thereof; a casing for the wheel member attached a printed circuit board having a plurality of illuminants; and a reflective frame member having enclosure walls expanding outwardly to a forward direction from a central part thereof, having a plurality of windows set the illuminants thereinto, characterized in that the illuminants arranged so as to project inside a center part of the reflective frame member; and a projection part, having a reflective face, reflecting the light emitted by the illuminants toward at least the symbol from the inner side of the wheel member so that it can irradiate a reflex of a reflective frame member equally without spots to the symbol of wheel member and can reduce the number of the parts.
    Type: Application
    Filed: May 13, 2003
    Publication date: October 14, 2004
    Inventor: Fumio Inoue
  • Patent number: 6791623
    Abstract: An image display system includes a memory for storing at least one scanning line of an inputted video signal of the interlace scanning system, and reading means for repeating to read the video signal of one scanning line from the memory at a speed which is n (n is an integer of 2 or more) times of the writing speed of the video signal for the memory for a horizontal scanning period which is 1/n of the writing period and to stop reading for a horizontal scanning period of the remaining (n−1)/n for each scanning line of one field which is sequentially inputted and reading each scanning line so that the continuous fields interpolate the period of stopping of reading from the memory each other.
    Type: Grant
    Filed: November 2, 1999
    Date of Patent: September 14, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Kouzou Masuda, Ikuya Arai, Sadao Tsuruga, Jiro Kawasaki, Tsuyoshi Sano, Tamotsu Nagabayashi, Ryuuichi Someya, Fumio Inoue, Kouji Kitou, Yasuhiro Imai, Masatoshi Hirose
  • Publication number: 20040110319
    Abstract: A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.
    Type: Application
    Filed: November 10, 2003
    Publication date: June 10, 2004
    Applicant: Hitachi Chemical Company, Ltd.
    Inventors: Naoki Fukutomi, Yoshiaki Tsubomatsu, Fumio Inoue, Toshio Yamazaki, Hirohito Ohhata, Shinsuke Hagiwara, Noriyuki Taguchi, Hiroshi Nomura
  • Patent number: 6746897
    Abstract: A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: June 8, 2004
    Inventors: Naoki Fukutomi, Yoshiaki Tsubomatsu, Fumio Inoue, Toshio Yamazaki, Hirohito Ohhata, Shinsuke Hagiwara, Noriyuki Taguchi, Hiroshi Nomura