Patents by Inventor Fumio Inoue

Fumio Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040018869
    Abstract: A symbol display device includes a stepping motor, a drive gear attached to a drive shaft of the stepping motor, a reduction gear meshing with the drive gear, and a reel fixed to the reduction gear. The stepping motor, the drive gear and the reduction gear are contained in the housing disposed in the reel. As a pitch radius of the reduction gear is set so as to be larger than that of the drive gear, a velocity of rotation of the reduction gear is lower than that of the drive gear. The stepping motor causes to rotate the reel with reduction of the rotational velocity.
    Type: Application
    Filed: April 10, 2003
    Publication date: January 29, 2004
    Inventor: Fumio Inoue
  • Publication number: 20030146571
    Abstract: A symbol display device includes a stepping motor, a drive gear attached to a drive shaft of the stepping motor, a reduction gear meshing with the drive gear, and a reel fixed to the reduction gear. The stepping motor, the drive gear and the reduction gear are contained in the housing disposed in the reel. As a pitch radius of the reduction gear is set so as to be larger than that of the drive gear, a velocity of rotation of the reduction gear is lower than that of the drive gear. The stepping motor causes to rotate the reel with reduction of the rotational velocity.
    Type: Application
    Filed: June 5, 2002
    Publication date: August 7, 2003
    Applicant: WING CO., LTD.
    Inventor: Fumio Inoue
  • Patent number: 6540227
    Abstract: A case of a stepping motor is divided by a partition. One of divided portions of the case contains a rotor and a stator of the stepping motor. A small-sized drive gear is fixed to a drive shaft integrally rotated with the rotor. The drive gear is meshed with a larger gear of a transmission gear. This transmission gear includes a smaller gear integrally rotated with the larger gear. The smaller gear is meshed with a large-sized output gear fixed to an output shaft of the stepping motor. Two pairs of the reduction gear mechanisms transmit a rotation of the drive shaft to the output shaft in a reduced state.
    Type: Grant
    Filed: May 30, 2001
    Date of Patent: April 1, 2003
    Assignee: Wing Co., Ltd.
    Inventor: Fumio Inoue
  • Publication number: 20020180147
    Abstract: A case of a stepping motor is divided by a partition. One of divided portions of the case contains a rotor and a stator of the stepping motor. A small-sized drive gear is fixed to a drive shaft integrally rotated with the rotor. The drive gear is meshed with a larger gear of a transmission gear. This transmission gear includes a smaller gear integrally rotated with the larger gear. The smaller gear is meshed with a large-sized output gear fixed to an output shaft of the stepping motor. Two pairs of the reduction gear mechanisms transmit a rotation of the drive shaft to the output shaft in a reduced state.
    Type: Application
    Filed: May 30, 2001
    Publication date: December 5, 2002
    Applicant: Wing Co., Ltd.
    Inventor: Fumio Inoue
  • Publication number: 20020094606
    Abstract: A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.
    Type: Application
    Filed: January 8, 2002
    Publication date: July 18, 2002
    Applicant: Hitachi Chemical Company, Ltd.
    Inventors: Naoki Fukutomi, Yoshiaki Tsubomatsu, Fumio Inoue, Toshio Yamazaki, Hirohito Ohhata, Shinsuke Hagiwara, Noriyuki Taguchi, Hiroshi Nomura
  • Publication number: 20020039808
    Abstract: A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.
    Type: Application
    Filed: October 23, 2001
    Publication date: April 4, 2002
    Applicant: Hitachi Chemical Company, Ltd.
    Inventors: Naoki Fukutomi, Yoshiaki Tsubomatsu, Fumio Inoue, Toshio Yamazaki, Hirohito Ohhata, Shinsuke Hagiwara, Noriyuki Taguchi, Hiroshi Nomura
  • Publication number: 20020039193
    Abstract: A search is conducted through a registered large advertising list to judge whether there are at least two large ad advertisers with credit of at least 1 in the large ad list. If not, free printing is inhibited. If so, a search is made for small ad advertisers to check if there are at least three small ad advertisers with credit of at least 1. If not, free printing is inhibited. If so, free printing is allowed. In this way, an image output system can be provided capable of producing a high image quality print with a sub image added thereto at no charge or a small charge by imposing a certain limit.
    Type: Application
    Filed: February 5, 2001
    Publication date: April 4, 2002
    Inventors: Shoji Kondo, Fumio Inoue
  • Patent number: 6365432
    Abstract: A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.
    Type: Grant
    Filed: January 19, 2000
    Date of Patent: April 2, 2002
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Naoki Fukutomi, Yoshiaki Tsubomatsu, Fumio Inoue, Toshio Yamazaki, Hirohito Ohhata, Shinsuke Hagiwara, Noriyuki Taguchi, Hiroshi Nomura
  • Patent number: 6331729
    Abstract: In the present invention, an insulating film adhesive material is attached onto the wirings in the form of a tent so that an empty space communicating with a vent hole is provided. Use of this chip-supporting substrate makes it possible to produce small-sized semiconductor packages preventive of package cracking and having a high reliability, because the function of the vent hole is not damaged and also gases and water vapor which are generated from the insulating film adhesive material at the time of reflowing can be driven off surely outside the package.
    Type: Grant
    Filed: August 10, 1999
    Date of Patent: December 18, 2001
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Masami Yusa, Toshihiko Kato, Fumio Inoue, Shigeki Ichimura
  • Patent number: 6236108
    Abstract: A semiconductor packaging chip-supporting substrate of the present invention comprises an insulating supporting substrate, wiring provided on the substrate, and an insulating film provided on the wiring. The wiring each have i) an inner connection that connects to a semiconductor chip electrode and ii) a semiconductor chip-mounting region. An opening is also provided in the insulating supporting substrate at its part where each of the wiring is formed on the insulating supporting substrate, which is the part where an outer connection conducting to the inner connection is provided. The insulating film is formed at the part on which the semiconductor chip is mounted, covering the semiconductor chip-mounting region of the wiring.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: May 22, 2001
    Assignees: Hitachi Chemical Company, Ltd., Sharp Corporation
    Inventors: Yoshiki Sota, Koji Miyata, Toshio Yamazaki, Fumio Inoue, Hidehiro Nakamura, Yoshiaki Tsubomatsu, Yasuhiko Awano, Shigeki Ichimura, Masami Yusa, Yorio Iwasaki
  • Patent number: 6223429
    Abstract: To provide a highly reliable semiconductor device structure that enables cost reduction in the production of packages, inclusive of the cost for chips, and may cause less changes in connection resistance even under conditions of a long-term environmental resistance test. In a semiconductor device comprising a semiconductor chip face-down bonded to a wiring board, it has a structure wherein projecting metal portions are provided at the opposing wiring board terminals without forming bumps on bonding pads of the chip, the whole chip surface is bonded with an organic, anisotropic conductive adhesive material, and the whole or at least an edge of the back of the chip is covered with a sealing material.
    Type: Grant
    Filed: July 30, 1998
    Date of Patent: May 1, 2001
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Aizou Kaneda, Masaaki Yasuda, Itsuo Watanabe, Tomohisa Ohta, Fumio Inoue, Yoshiaki Tsubomatsu, Toshio Yamazaki, Hiroto Ohata, Kenzo Takemura, Akira Nagai, Osamu Watanabe, Naoyuki Shiozawa, Kazuyoshi Kojima, Toshiaki Tanaka, Kazunori Yamamoto
  • Patent number: 6064111
    Abstract: A semiconductor packaging chip-supporting substrate of the present invention comprises an insulating supporting substrate, wiring provided on the substrate, and an insulating film provided on the wiring. The wiring each have i) an inner connection that connects to a semiconductor chip electrode and ii) a semiconductor chip-mounting region. An opening is also provided in the insulating supporting a substrate at its part where each of the wiring is formed on the insulating supporting substrate, which is the part where an outer connection conducting to the inner connection is provided. The insulating film is formed at the part on which the semiconductor chip is mounted, covering the semiconductor chip-mounting region of the wiring.
    Type: Grant
    Filed: July 31, 1997
    Date of Patent: May 16, 2000
    Assignees: Hitachi Company, Ltd., Sharp Corporation
    Inventors: Yoshiki Sota, Koji Miyata, Toshio Yamazaki, Fumio Inoue, Hidehiro Nakamura, Yoshiaki Tsubomatsu, Yasuhiko Awano, Shigeki Ichimura, Masami Yusa, Yorio Iwasaki
  • Patent number: 6006353
    Abstract: A plurality of generator polynomials are prepared for error correction and stored in a table by assigning a specific table number to each generator polynomial. Each generator polynomial provides a different error correction capability so that a different number of error correction bits are added to each set of transmission data. For radio communication, an electric field intensity is first measured, and in accordance with this electric field intensity, a generator polynomial to be used at that time for error correction calculation is determined. It is therefore possible to change the number of error correction bits in accordance with the environment at that time and to perform efficient error correction. For example, if a base station is in a near area, an error rate is small so that the number of addition bits is reduced.
    Type: Grant
    Filed: October 8, 1997
    Date of Patent: December 21, 1999
    Assignee: Matsushita Electric Industrial Co. Ltd.
    Inventor: Fumio Inoue
  • Patent number: 5976912
    Abstract: A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.
    Type: Grant
    Filed: September 18, 1996
    Date of Patent: November 2, 1999
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Naoki Fukutomi, Yoshiaki Tsubomatsu, Fumio Inoue, Toshio Yamazaki, Hirohito Ohhata, Shinsuke Hagiwara, Noriyuki Taguchi, Hiroshi Nomura
  • Patent number: 5978041
    Abstract: An image display system includes a display circuit which displays an image composed of a plurality of sub-images, an input circuit which inputs a certain image signal including at least one sub-image embedded in the certain image signal which is provided by at least one of fields and frames, a designating circuit which designates timings of composition positions of the sub-image on scan lines of the certain image, and one control circuit which controls at least one of an amplitude level and a DC level of image signals corresponding to an area of the sub-image detected by the timing designated by the designating circuit.
    Type: Grant
    Filed: October 24, 1995
    Date of Patent: November 2, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Kouzou Masuda, Ikuya Arai, Sadao Tsuruga, Jiro Kawasaki, Tsuyoshi Sano, Tamotsu Nagabayashi, Ryuuichi Someya, Fumio Inoue, Kouji Kitou, Yasuhiro Imai, Masatoshi Hirose
  • Patent number: 5758940
    Abstract: A liquid crystal projection display capable of functioning at a high light capturing efficiency and a high relative corner illuminance comprises a light source means including a light source, a liquid crystal panel means, a projection lens means and a screen means. A liquid lens formed by sealing a liquid in a space between opposite transparent members is disposed near the light source or the real image of the light source to enhance the relative corner illuminance without reducing the light capturing efficiency by multiplying the angle of divergence of light rays emitted by the light source by the reciprocal of the refractive index of the liquid. A first optical system disposed on the entrance side of the liquid crystal panel is provided with a relative corner illuminance enhancing means comprising a first light converging means disposed relatively near to the light source means, and a second light converging means disposed relatively remote from the light source means.
    Type: Grant
    Filed: July 16, 1996
    Date of Patent: June 2, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Ogino, Yoshiaki Iwahara, Takeo Yamada, Shigeru Mori, Fumio Inoue, Akio Yamamoto
  • Patent number: 5557342
    Abstract: A video display system that includes a housing has arranged thereon a plurality of video input terminals for receiving a plurality of video signals having different scanning frequencies. An expansion/compression processing circuit replaceably mounted on the housing receives and expands/compresses the plurality of video signals and produces at least one video signal expanded/compressed in synchronism with a sync signal selected by a sync switching circuit. At least one of the video signals is synthesized with another video signal, and the synthesized video signal is produced by a video signal synthesis circuit. A video signal from the video signal synthesis circuit is used to generate a video display signal in synchronism with the sync signal. This video display signal is applied to a display. At least one such video display system, an AV controller, a central control console and a lecture table are combined to realize a screen display system.
    Type: Grant
    Filed: April 19, 1995
    Date of Patent: September 17, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Eto, Hiroyuki Urata, Fumio Inoue, Masanori Ogino, Atsushi Maruyama, Kiyoshi Yamamoto
  • Patent number: 5541665
    Abstract: In order to enable sampling of high definition still video signals in addition to common video signals, a function is added for sampling video signals with every other plurality of picture elements as an interval to an image processing apparatus without using a sampling circuit which requires high speed operations. The invention is also intended to change over between two circuits that is, a circuit for using a picture element clock regenerated by a PLL circuit as a sampling clock for analog to digital converters and a circuit for using a clock obtained by dividing the picture element clock as a sampling clock for the analog to digital converters to sample video signals with every other plurality of picture elements as an interval. Thus, it is possible to carry out sampling of high definition video signals with high frequencies in addition to common video signals without necessity of raising the operating speed of the sampling circuit.
    Type: Grant
    Filed: December 22, 1994
    Date of Patent: July 30, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Urata, Masahiro Eto, Atsushi Maruyama, Fumio Inoue, Masanori Ogino, Kiyoshi Yamamoto, Kazutaka Naka, Masaaki Iwanaga
  • Patent number: 5537171
    Abstract: A liquid crystal projection display capable of functioning at a high light capturing efficiency and a high relative corner illuminance comprises a light source means including a light source, a liquid crystal panel means, a projection lens means and a screen means. A liquid lens formed by sealing a liquid in a space between opposite transparent members is disposed near the light source or the real image of the light source to enhance the relative corner illuminance without reducing the light capturing efficiency by multiplying the angle of divergence of light rays emitted by the light source by the reciprocal of the refractive index of the liquid. A first optical system disposed on the entrance side of the liquid crystal panel is provided with a relative corner illuminance enhancing means comprising a first light converging means disposed relatively near to the light source means, and a second light converging means disposed relatively remote from the light source means.
    Type: Grant
    Filed: October 11, 1994
    Date of Patent: July 16, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Ogino, Yoshiaki Iwahara, Takeo Yamada, Shigeru Mori, Fumio Inoue, Akio Yamamoto
  • Patent number: 5517210
    Abstract: A multi-scan type display apparatus with pointer function includes a multi-scan type display unit for displaying a plurality of kinds of main picture signals having different numbers of scanning lines and a pointer position identifying signal generating circuit for generating a pointer position identifying signal. The pointer position identifying signal generating circuit transfers the pointer position identifying signal to the multi-scan type display unit, the multi-scan type display unit includes a universal vertical position address signal generating circuit, a horizontal position address signal generating circuit, a pointer signal generating circuit and a superimposing circuit.
    Type: Grant
    Filed: September 2, 1993
    Date of Patent: May 14, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Ogino, Yasuharu Tamuro, Miyuki Ikeda, Fumio Inoue