Abstract: A semiconductor integrated circuit device is dislosed for self-monitoring presence/absence of a data flow and transmitting the data on the basis of the result of the monitoring. The semiconductor integrated circuit device comprises a plurality of data paths each further comprising at least two logic-circuit blocks. One of the data paths have data-arrival detector for detecting arrival of data and components on the other data paths operate synchronously with those on the data path having the data-arrival detector.

Abstract: The object of the present invention is to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor.

Abstract: The object of the present invention is to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor.

Abstract: A floating-point arithmetic processing apparatus has a circuit for generating a limit value for normalization shift by subtracting an exponent of the minimum value of a normalized number from a value of an exponent of an intermediate result, and a circuit for generating, as a normalization shift number, smaller one of a shift number necessary for making the mantissa of the intermediate result a normalized number and the limit value for normalization shift. The floating-point arithmetic processing apparatus further has a circuit having a circuit for detecting a condition for overflow before the rounding process and a circuit for generating a value in the case of overflow, so that a predetermined value is delivered as a final result only when the overflow condition is detected before the rounding process but in the other case, a result obtained by performing the normalization process and the rounding process is delivered.

Abstract: A semiconductor integrated circuit device using precharge circuits free from the influence of a phase difference skew is provided. Each of the precharge circuits is controlled by a clock signal such that an arbitrary node in the circuit is precharged during a low level period or a high level period of the clock signal and the precharge circuit is operative during a high level period or a low level period of the clock signal. A first precharge circuit and a second precharge circuit having the same operational functions are arranged in parallel, and controlled by their respective clock signals to perform complementary operations, wherein the second precharge circuit is in an active period when the first precharge circuit is in a precharge period, and the second precharge circuit is in a precharge period when the first precharge circuit is in an active period.

Abstract: A semiconductor integrated circuit device is provided which includes at least one first functional circuit block which receives an input signal and executes a logical operation to output an output signal as a result. At least one second functional circuit block is connected in parallel with the first functional circuit block. The second functional circuit block also responds to an input signal to execute a logical operation and output an output signal as a result. The first and second functional circuit blocks are connected to one another such that the second functional circuit block will operate synchronously with the first functional circuit block. More specifically, the first functional circuit block is arranged to control an output timing of the second functional circuit block.

Abstract: An information processing system has a plurality of processor circuits, each of the processor circuits including internal circuits and an internal processing result outputting circuit, the system having an internal data selection circuit connected to each of the processor circuits and at least one fault detection circuit. The internal processing result outputting circuit of each of the processor circuits outputs respective result data processed by respective ones of the internal circuits in the processor circuit. Each of the internal data selection circuit selects and outputs one selected result data output from the internal processing result outputting circuit of each of the processor circuits, at a predetermined timing. The fault detection circuit outputs a result of a comparison among the data selected by the respective internal data selection circuits of the processor circuits or among the data output at each predetermined timing by the processor circuits.

Abstract: The present invention is intended to provide a conventional circuit apparatus which is highly tolerant to noises and operates at a higher speed than a completely complementary static CMOS circuit. To achieve this, circuit apparatus according to the present invention is provided with a plurality of CMOS static logic circuits which are series-connected and potential setting means which is connected to the output parts of these logic circuits and sets the outputs of the output parts to a low level in synchronization with a clock signal, thus propagating signals by operation of the NMOS circuit. In other words, a signal propagation delay occurs only when the N-type logic block conducts. Therefore circuit operation is speeded up and .alpha. particle noise and noises due to charge redistribution effect or leakage current can be prevented.

Abstract: A semiconductor integrated circuit device using precharge circuits free from the influence of a phase difference skew is provided. Each of the precharge circuits is controlled by a clock signal such that an arbitrary node in the circuit is precharged during a low level period or a high level period of the clock signal and the precharge circuit is operative during a high level period or a low level period of the clock signal. A first precharge circuit and a second precharge circuit having the same operational functions are arranged in parallel, and controlled by their respective clock signals to perform complementary operations, wherein the second precharge circuit is in an active period when the first precharge circuit is in a precharge period, and the second precharge circuit is in a precharge period when the first precharge circuit is in an active period.

Abstract: To offer a floating-point addition/subtraction processing apparatus and a method thereof, capable of shortening the computation time, the floating-point calculation processing apparatus includes an approximate shift mount predicting unit for predicting a shift amount for normalization by using the input floating-point data to be addition/subtraction processed within an error of 1 bit, a shift error detecting unit for detecting a difference between the predicted shift amount and a correct shift amount, and an bit shifter for correcting a result, obtained by normalization using the predicted shift amount, by the detected difference of the two shift amounts, wherein a round-off determination and a shift amount calculation are processed in parallel before a normalization shift processing is executed.

Abstract: The object of the present invention is to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor.

Abstract: A semiconductor integrated circuit device having a plurality of logic circuits integrated on a semiconductor substrate is provided which can operate with a power source potential difference substantially less than 5 V. The logic circuit includes a bipolar transistor having a base and its collector-emitter current path coupled between a first power source terminal and an output terminal, together with at least one field effect transistor having its gate responsive to an input signal applied to an input terminal and its source-drain current path coupled between the first power source terminal and the base of the bipolar transistor. A semiconductor switch means is also provided which is responsive to the input signal applied to the input terminal for performing ON/OFF operations complementary to the ON/OFF operations of the bipolar transistor and which has a current path between its paired main terminals coupled between the output terminal and the second power source terminal.

Abstract: A semiconductor integrated circuit device is equipped with a series of data handling stages, at least one of which includes a plurality of functional blocks arranged in parallel, a connecting means for connecting the functional blocks to functional blocks in a subsequent data handling stage, and a detection means for detecting data flow along a first connection in the connecting means. The detection means is included within a control means which controls data flow through at least one other connection in the connecting means based on the detection of data flow through the first connection in the connecting means.

Abstract: A carry propagating device, provided on a single substrate, is constituted by groups of first and second MOS transistors, a third MOS transistor, a bipolar transistor and first and second impedance elements. An output of the carry propagating device is provided at the collector of the bipolar transistor and is connected to a first power supply terminal through the first impedance element, the emitter is connected to a second power supply terminal through the second impedance element, and the base is connected to a fixed potential source. The first MOS transistors are connected in series between the emitter of the bipolar transistor and the second power supply terminal through the third MOS transistor controlled by a carry signal.

Abstract: In a system wherein a plurality of semiconductor integrated circuit devices are coexistent and wherein a plurality of supply potential lines are laid, the main power sources of a TTL interface LSI and an ECL interface LSI are shared so as to reduce the number of supply potential lines. Besides, in a case where an LSI, for example, BiCMOS LSI to interface with both the TTL and ECL interface LSI's has a device withstand voltage of about 3 V, it is permitted to interface with both the LSI's across the supply voltage .vertline.5 V.vertline. of the main power source of the TTL interface LSI and the supply voltage .vertline.2 V.vertline. of the power source of the emitter follower portion of the ECL interface LSI because the supply voltages have a difference of 3 V.

Abstract: A semiconductor integrated circuit device with a built-in memory circuit group is disclosed, wherein wiring is started from a data terminal position near a data exchange portion of a memory circuit group to reduce the length of a wiring. Accordingly, an operation speed can be improved by the reduction of wiring capacitance and a ratio of unwired wirings can be reduced by reduction of an occupying ratio of wiring channels.

Abstract: A semiconductor integrated circuit device is arranged to have a plurality of logic circuit blocks, a data signal path for interconnecting logic circuit blocks and for providing a function of interfacing a current-driven signal. The logic circuit block on a signal output side includes an output circuit connected to the data signal path and a switching element formed of an NMOS transistor for controlling current flowing through the data signal path in response to an input signal applied to an input terminal of the output circuit. The logic circuit block on a signal input side includes an input circuit connected to the data signal path. The input circuit includes a bipolar transistor having an emitter connected to a constant current source, a collector forming an output terminal, and a base set at a fixed potential. The data signal path led from the output circuit is connected to the emitter of the bipolar transistor.

Abstract: A semiconductor integrated circuit device having a plurality of logic circuits integrated on a semiconductor substrate is provided which can operate with a power source potential difference substantially less than 5 V. The logic circuit includes a bipolar transistor having a base and its collector-emitter current path coupled between a first power source terminal and an output terminal, together with at least one field effect transistor having its gate responsive to an input signal applied to an input terminal and its source-drain current path coupled between the first power source terminal and the base of the bipolar transistor. A semiconductor switch means is also provided which is responsive to the input signal applied to the input terminal for performing ON/OFF operations complementary to the ON/OFF operations of the bipolar transistor and which has a current path between its paired main terminals coupled between the output terminal and the second power source terminal.

Abstract: A semiconductor integrated circuit device with a built-in memory circuit group is disclosed, wherein wiring is started from a data terminal position near a data exchange portion of a memory circuit group to reduce the length of a wiring. Accordingly, an operation speed can be improved by the reduction of wiring capacitance and a ratio of unwired wirings can be reduced by reduction of an occupying ratio of wiring channels.

Abstract: A semiconductor integrated circuit device having a plurality of logic circuits integrated on a semiconductor substrate is provided which can operate with a power source potential difference substantially less than 5V. The logic circuit includes a bipolar transistor having a base and its collector-emitter current path coupled between a first power source terminal and an output terminal, together with at least one field effect transistor having its gate responsive to an input signal applied to an input terminal and its source-drain current path coupled between the first power source terminal and the base of the bipolar transistor. A semiconductor switch means is also provided which is responsive to the input signal applied to the input terminal for performing ON/OFF operations complementary to the ON/OFF operations of the bipolar transistor and which has a current path between its paired main terminals coupled between the output terminal and the second power source terminal.