Patents by Inventor Fumitaka Amano

Fumitaka Amano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220130852
    Abstract: A semiconductor structure includes a first alternating stack of first insulating layers and first electrically conductive layers having first stepped surfaces and located over a substrate, a second alternating stack of second insulating layers and second electrically conductive layers having second stepped surfaces, and memory opening fill structures extending through the alternating stacks. A contact via assembly is provided, which includes a first conductive via structure vertically extending from a top surface of one of the first electrically conductive layers through a subset of layers within the second alternating stack and through the second retro-stepped dielectric material portion, an insulating spacer located within an opening through the subset of layers, and a second conductive via structure laterally surrounding the insulating spacer and contacting a second electrically conductive layer.
    Type: Application
    Filed: October 27, 2020
    Publication date: April 28, 2022
    Inventors: Yuji TOTOKI, Fumitaka AMANO
  • Patent number: 11309402
    Abstract: A semiconductor structure includes a semiconductor channel of a first conductivity type located between a first and second active regions having a doping of a second conductivity type that is opposite of the first conductivity type, a gate stack structure that overlies the semiconductor channel, and includes a gate dielectric and a gate electrode, a first metal-semiconductor alloy portion embedded in the first active region, and a first composite contact via structure in contact with the first active region and the first metal-semiconductor alloy portion, and contains a first tubular liner spacer including a first annular bottom surface, a first metallic nitride liner contacting an inner sidewall of the first tubular liner spacer and having a bottom surface that is located above a horizontal plane including bottom surface of the first tubular liner spacer, and a first metallic fill material portion embedded in the first metallic nitride liner.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: April 19, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Fumitaka Amano, Yosuke Kita
  • Patent number: 11296112
    Abstract: A semiconductor structure includes a doped semiconductor material portion, a metal-semiconductor alloy portion contacting the doped semiconductor material portion, a device contact via structure in direct contact with the metal-semiconductor alloy portion, and at least one dielectric material layer laterally surrounding the device contact via structure. The device contact via structure includes a barrier stack and a conductive fill material portion. The barrier stack includes at least two metal nitride layers and at least one nitrogen-containing material layer containing nitrogen and an element selected from silicon or boron.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: April 5, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Fumitaka Amano
  • Publication number: 20210280686
    Abstract: A semiconductor structure includes a semiconductor channel of a first conductivity type located between a first and second active regions having a doping of a second conductivity type that is opposite of the first conductivity type, a gate stack structure that overlies the semiconductor channel, and includes a gate dielectric and a gate electrode, a first metal-semiconductor alloy portion embedded in the first active region, and a first composite contact via structure in contact with the first active region and the first metal-semiconductor alloy portion, and contains a first tubular liner spacer including a first annular bottom surface, a first metallic nitride liner contacting an inner sidewall of the first tubular liner spacer and having a bottom surface that is located above a horizontal plane including bottom surface of the first tubular liner spacer, and a first metallic fill material portion embedded in the first metallic nitride liner.
    Type: Application
    Filed: March 5, 2020
    Publication date: September 9, 2021
    Inventors: Fumitaka AMANO, Yosuke KITA
  • Publication number: 20200258909
    Abstract: A semiconductor structure includes a doped semiconductor material portion, a metal-semiconductor alloy portion contacting the doped semiconductor material portion, a device contact via structure in direct contact with the metal-semiconductor alloy portion, and at least one dielectric material layer laterally surrounding the device contact via structure. The device contact via structure includes a barrier stack and a conductive fill material portion. The barrier stack includes at least two metal nitride layers and at least one nitrogen-containing material layer containing nitrogen and an element selected from silicon or boron.
    Type: Application
    Filed: April 28, 2020
    Publication date: August 13, 2020
    Inventor: Fumitaka AMANO
  • Patent number: 10662522
    Abstract: A method of forming a metallic material on a substrate includes coating a chuck of a metallic material deposition chamber with an elemental metal coating, loading a substrate onto the chuck of the metallic material deposition chamber, and depositing an elemental metal layer on the substrate by thermal decomposition of a metal precursor gas including metal compound molecules. Each of the metal compound molecules includes an atom of the elemental metal and a first number of atoms of a non-metallic element. The metal compound molecules react with atoms of the elemental metal in the metal coating to generate molecules of an intermediate reaction compound including an atom of the elemental metal and a second number of atoms of the non-metallic element, the second number of atoms being less than the first number of atoms. The metal layer on the substrate is formed by thermal decomposition of the intermediate reaction compound.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: May 26, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Fumitaka Amano
  • Publication number: 20200149164
    Abstract: A deposition apparatus includes a deposition chamber including a chuck and a vacuum enclosure connected to a vacuum pump system and enclosing the chuck, and a gas manifold configured to provide process gases to the vacuum enclosure, the process gases including a metal precursor gas. The gas manifold includes an in-line intermediate reaction compound generator that includes an inlet orifice into which the metal precursor gas is supplied and an exhaust orifice from which an intermediate reaction compound derived from the metal precursor gas exits into a gas inlet of the vacuum enclosure. The in-line intermediate reaction compound generator includes at least one metal portion connected to a heater configured to maintain the at least one metal portion at a temperature greater than 300 degrees Celsius during operation.
    Type: Application
    Filed: November 8, 2018
    Publication date: May 14, 2020
    Inventor: Fumitaka AMANO
  • Publication number: 20200149153
    Abstract: A method of forming a metallic material on a substrate includes coating a chuck of a metallic material deposition chamber with an elemental metal coating, loading a substrate onto the chuck of the metallic material deposition chamber, and depositing an elemental metal layer on the substrate by thermal decomposition of a metal precursor gas including metal compound molecules. Each of the metal compound molecules includes an atom of the elemental metal and a first number of atoms of a non-metallic element. The metal compound molecules react with atoms of the elemental metal in the metal coating to generate molecules of an intermediate reaction compound including an atom of the elemental metal and a second number of atoms of the non-metallic element, the second number of atoms being less than the first number of atoms. The metal layer on the substrate is formed by thermal decomposition of the intermediate reaction compound.
    Type: Application
    Filed: November 8, 2018
    Publication date: May 14, 2020
    Inventor: Fumitaka AMANO
  • Publication number: 20200105595
    Abstract: A method of forming a memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate forming memory stack structures through the alternating stack, forming a first backside trench and a second backside trench through the alternating stack, forming backside recesses by removing the sacrificial material layers, depositing a backside blocking dielectric layer after formation of the backside recesses, forming a liner that a lesser lateral extent than a lateral distance between the first backside trench and the second backside trench; and selectively growing a metal from surfaces of the liners while either not growing or growing at a lower rate the metal from surfaces of the backside recesses that are not covered by the liners.
    Type: Application
    Filed: November 19, 2019
    Publication date: April 2, 2020
    Inventors: Rahul SHARANGPANI, Raghuveer S. MAKALA, Fei ZHOU, Adarsh RAJASHEKHAR, Senaka Krishna KANAKAMEDALA, Fumitaka AMANO, Genta MIZUNO
  • Patent number: 10529620
    Abstract: A method of forming a memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate forming memory stack structures through the alternating stack, forming a first backside trench and a second backside trench through the alternating stack, forming backside recesses by removing the sacrificial material layers, depositing a backside blocking dielectric layer after formation of the backside recesses, forming a liner that a lesser lateral extent than a lateral distance between the first backside trench and the second backside trench; and selectively growing a metal from surfaces of the liners while either not growing or growing at a lower rate the metal from surfaces of the backside recesses that are not covered by the liners.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: January 7, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Fei Zhou, Adarsh Rajashekhar, Senaka Krishna Kanakamedala, Fumitaka Amano, Genta Mizuno
  • Patent number: 10381372
    Abstract: Void formation in tungsten lines in a three-dimensional memory device can be prevented by providing polycrystalline aluminum oxide liners in portions of lateral recesses that are laterally spaced from backside trenches by a distance grater than a predefined lateral offset distance. Tungsten nucleates on the polycrystalline aluminum oxide liners prior to nucleating on a metallic liner layer. Thus, tungsten layers can be deposited from the center portion of each backside recess, and the growth of tungsten can proceed toward the backside trenches. By forming the tungsten layers without voids, structural integrity of the three-dimensional memory device can be enhanced.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: August 13, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Fumitaka Amano, Takashi Arai, Genta Mizuno, Shigehisa Inoue, Naoki Takeguchi, Takashi Hamaya
  • Patent number: 10361213
    Abstract: Memory stack structures are formed through an alternating stack of insulating layers and sacrificial material layers. Backside recesses are formed by removal of the sacrificial material layers selective to the insulating layers and the memory stack structures. A barrier layer stack including a crystalline electrically conductive barrier layer and an amorphous barrier layer is formed in the backside recesses prior to formation of a metal fill material layer.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: July 23, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Fumitaka Amano, Raghuveer S. Makala, Fei Zhou, Keerti Shukla
  • Patent number: 10276583
    Abstract: Word lines for a three-dimensional memory device can be formed by forming a stack of alternating layers comprising insulating layers and sacrificial material layers and memory stack structures vertically extending therethrough. Backside recesses are formed by removing the sacrificial material layers through a backside via trench. A metal silicide layer and metal portion are formed in the backside recesses to form the word lines including a metal portion, a metal silicide layer, and optionally, a silicon-containing layer.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: April 30, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Fumitaka Amano, Raghuveer S. Makala, Adarsh Rajashekhar, Fei Zhou
  • Publication number: 20180331118
    Abstract: A semiconductor structure includes a doped semiconductor material portion, a metal-semiconductor alloy portion contacting the doped semiconductor material portion, a device contact via structure in direct contact with the metal-semiconductor alloy portion, and at least one dielectric material layer laterally surrounding the device contact via structure. The device contact via structure includes a barrier stack and a conductive fill material portion. The barrier stack includes at least two metal nitride layers and at least one nitrogen-containing material layer containing nitrogen and an element selected from silicon or boron.
    Type: Application
    Filed: May 12, 2017
    Publication date: November 15, 2018
    Inventor: Fumitaka AMANO
  • Patent number: 10115735
    Abstract: A semiconductor device includes a silicon surface, a titanium silicide layer contacting the silicon surface, a first titanium nitride layer located over the titanium silicide layer, a titanium oxynitride layer contacting the first titanium nitride layer, a second titanium nitride layer contacting the titanium oxynitride layer, and a metal fill layer located over the second titanium nitride layer.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: October 30, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Fumitaka Amano, Kensuke Ishikawa, Shinya Inoue, Michiaki Sano
  • Publication number: 20180247954
    Abstract: A semiconductor device includes a silicon surface, a titanium silicide layer contacting the silicon surface, a first titanium nitride layer located over the titanium silicide layer, a titanium oxynitride layer contacting the first titanium nitride layer, a second titanium nitride layer contacting the titanium oxynitride layer, and a metal fill layer located over the second titanium nitride layer.
    Type: Application
    Filed: June 8, 2017
    Publication date: August 30, 2018
    Inventors: Fumitaka Amano, Kensuke Ishikawa, Shinya Inoue, Michiaki Sano
  • Publication number: 20180090373
    Abstract: A method of forming a memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate forming memory stack structures through the alternating stack, forming a first backside trench and a second backside trench through the alternating stack, forming backside recesses by removing the sacrificial material layers, depositing a backside blocking dielectric layer after formation of the backside recesses, forming a liner that a lesser lateral extent than a lateral distance between the first backside trench and the second backside trench; and selectively growing a metal from surfaces of the liners while either not growing or growing at a lower rate the metal from surfaces of the backside recesses that are not covered by the liners.
    Type: Application
    Filed: December 4, 2017
    Publication date: March 29, 2018
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Fei Zhou, Adarsh Rajashekhar, Senaka Krishna Kanakamedala, Fumitaka Amano, Genta Mizuno
  • Patent number: 9929174
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures including a memory film and a vertical semiconductor channel are formed through the alternating stack in an array configuration. Backside trenches extending along a lengthwise direction are formed through the alternating stack. Backside recesses are formed by removing the sacrificial material layers. Filling of the backside recesses with electrically conductive layers can be performed without voids or with minimal voids by arranging the memory stack structures with a non-uniform pitch. The non-uniform pitch may be along the direction perpendicular to the lengthwise direction such that the nearest neighbor distance among the memory stack structures is at a minimum between the backside trenches. Alternatively or additionally, the pitch may be modulated along the lengthwise direction to provide wider spacing regions that extend perpendicular to the lengthwise direction.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: March 27, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yuki Mizutani, Hiroyuki Ogawa, Fumiaki Toyama, Masaaki Higashitani, Fumitaka Amano, Kota Funayama, Akihiro Ueda
  • Publication number: 20180033646
    Abstract: Word lines for a three-dimensional memory device can be formed by forming a stack of alternating layers comprising insulating layers and sacrificial material layers and memory stack structures vertically extending therethrough. Backside recesses are formed by removing the sacrificial material layers through a backside via trench. A metal silicide layer and metal portion are formed in the backside recesses to form the word lines including a metal portion, a metal silicide layer, and optionally, a silicon-containing layer.
    Type: Application
    Filed: October 11, 2017
    Publication date: February 1, 2018
    Inventors: Rahul SHARANGPANI, Fumitaka AMANO, Raghuveer S. MAKALA, Adarsh RAJASHEKHAR, Fei ZHOU
  • Publication number: 20180019256
    Abstract: Void formation in tungsten lines in a three-dimensional memory device can be prevented by providing polycrystalline aluminum oxide liners in portions of lateral recesses that are laterally spaced from backside trenches by a distance grater than a predefined lateral offset distance. Tungsten nucleates on the polycrystalline aluminum oxide liners prior to nucleating on a metallic liner layer. Thus, tungsten layers can be deposited from the center portion of each backside recess, and the growth of tungsten can proceed toward the backside trenches. By forming the tungsten layers without voids, structural integrity of the three-dimensional memory device can be enhanced.
    Type: Application
    Filed: October 24, 2016
    Publication date: January 18, 2018
    Inventors: Fumitaka AMANO, Takashi ARAI, Genta MIZUNO, Shigehisa INOUE, Naoki TAKEGUCHI, Takashi HAMAYA