Abstract: The present invention provides a transistor and a method for forming the same. The method includes: providing a semiconductor substrate having a semiconductor layer formed thereon, the semiconductor layer and the semiconductor substrate having different crystal orientations; forming a dummy gate structure on the semiconductor layer; forming a source region and a drain region in the semiconductor substrate and the semiconductor layer and at opposite sides of the dummy gate structure; forming an interlayer dielectric layer on the semiconductor layer, which is substantially flush with the dummy gate structure; removing the dummy gate structure and the semiconductor layer beneath the dummy gate structure, forming an opening in the interlayer dielectric layer and the semiconductor layer, the semiconductor substrate being exposed at a bottom of the opening; forming a metal gate structure in the opening. Saturation current of the transistor is raised, and performance of a semiconductor device is promoted.

Abstract: The invention provides a phase change memory and a method for forming the phase change memory. The phase change memory includes a storage region and a peripheral circuit region. The peripheral circuit region has a peripheral substrate, a plurality of peripheral shallow trench isolation (STI) units in the peripheral substrate, and at least one MOS transistor on the peripheral substrate and between the peripheral STI units. The storage region has a storage substrate, an N-type ion buried layer on the storage substrate, a plurality of vertical LEDs on the N-type ion buried layer, a plurality of storage shallow trench isolation (STI) units between the vertical LEDs, and a plurality of phase change layers on the vertical LED and between the storage STI units. The storage STI units have thickness substantially equal to thickness of the vertical LEDs. The peripheral STI units have thickness substantially equal to thickness of the storage STI units. The N-type conductive region contains SiC.

Abstract: A device having thin-film transistor (TFT) floating gate memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N+ polysilicon layer on a diffusion barrier layer which is on a first conductive layer. The N+ polysilicon layer has a second surface substantially co-planar with the first surface. Additionally, the device includes a P? polysilicon layer overlying the co-planar surface and a floating gate on the P? polysilicon layer. The floating gate is a low-pressure CVD-deposited silicon layer sandwiched by a bottom oxide tunnel layer and an upper oxide block layer. Moreover, the device includes at least one control gate made of a P+ polysilicon layer overlying the upper oxide block layer.

Abstract: A fin field effect transistor (Fin FET) and a method for forming the Fin FET are provided. In an exemplary method, the Fin FET can be formed by providing a dielectric layer on a semiconductor substrate. The dielectric layer and the semiconductor substrate can be etched to form a groove including a second sub-groove, formed through the dielectric layer, and a first sub-groove, formed in the semiconductor substrate and connected to the second sub-groove. A fin can then be formed in the groove. The fin can have a top surface higher than a top surface of the dielectric layer. A gate structure can then be formed at least partially around a length portion of the fin on the top surface of the dielectric layer.

Abstract: A device having thin-film transistor (TFT) silicon-aluminum oxide-silicon (SAS) memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N+ polysilicon layer on a diffusion barrier layer which is on a conductive layer. The N+ polysilicon layer has a second surface substantially co-planar with the first surface. Additionally, the device includes a P? polysilicon layer overlying the co-planar surface, an aluminum oxide layer overlying the P? polysilicon layer; and at least one control gate overlying the aluminum oxide layer. In a specific embodiment, the control gate is made of highly doped P+ polysilicon. A method for making the TFT SAS memory cell structure is provided and can be repeated to integrate the structure three-dimensionally.

Abstract: The invention discloses a semiconductor device which comprises an NMOS transistor and a PMOS transistor formed on a substrate; and grid electrodes, source cathode doped areas, drain doped areas, and side walls formed on two sides of the grid electrodes are arranged on the NMOS transistor and the PMOS transistor respectively. The device is characterized in that the side walls on the two sides of the grid electrode of the NMOS transistor possess tensile stress, and the side walls on the two sides of the grid electrode of the PMOS transistor possess compressive stress. The stress gives the side walls a greater role in adjusting the stress applied to channels and the source/drain areas, with the carrier mobility further enhanced and the performance of the device improved.

Abstract: The invention provides a phase change memory and a method for forming the phase change memory. The phase change memory includes a storage region and a peripheral circuit region. The peripheral circuit region has a peripheral substrate, a plurality of peripheral shallow trench isolation (STI) units in the peripheral substrate, and at least one MOS transistor on the peripheral substrate and between the peripheral STI units. The storage region has a storage substrate, an N-type ion buried layer on the storage substrate, a plurality of vertical LEDs on the N-type ion buried layer, a plurality of storage shallow trench isolation (STI) units between the vertical LEDs, and a plurality of phase change layers on the vertical LED and between the storage STI units. The storage STI units have thickness substantially equal to thickness of the vertical LEDs. The peripheral STI units have thickness substantially equal to thickness of the storage STI units. The N-type conductive region contains SiC.

Abstract: A semiconductor device manufacturing method includes providing a mask on a semiconductor member. The method further includes providing a dummy element to cover a portion of the mask that overlaps a first portion of the semiconductor member and to cover a second portion of the semiconductor member. The method further includes removing a third portion of the semiconductor member, which has not been covered by the mask or the dummy element. The method further includes providing a silicon compound that contacts the first portion of the semiconductor member. The method further includes removing the dummy element to expose and to remove the second portion of the semiconductor member. The method further includes forming a gate structure that overlaps the first portion of the semiconductor member. The first portion of the semiconductor member is used as a channel region and is supported by the silicon compound.

Abstract: A semiconductor device, and a method for manufacturing the same, comprises a source/drain region formed using a solid phase epitaxy (SPE) process to provide partially isolated source/drain transistors. Amorphous semiconductor material at the source/drain region is crystallized and then shrunk through annealing, to apply tensile stress in the channel direction.

Abstract: A semiconductor device includes a substrate having an active region, a gate structure on the active region, and spacers formed on opposite sides of the gate structure. The gate structure includes a gate dielectric layer on the active region, a metal gate on the gate dielectric layer, and sidewalls on both side surfaces of the gate structure. Each of the sidewalls is interposed between the metal gate and one of the spacers. The sidewalls include a self-assembly material. The gate dielectric layer includes a high-K material. The spacers include silicon nitride. The gate structure also includes a buffer layer interposed between the metal gate and the gate dielectric layer.

Abstract: A method for manufacturing a stressed CMOS device includes providing a substrate having a dummy gate and an insulating material layer formed thereon. The dummy gate is embedded in the insulating material layer. The method further includes removing the dummy gate to form a gate opening in the insulating material layer, and implanting carbon ions through the opening to form a stressed NMOS channel and/or implanting germanium/antimony/xenon ions to form a stressed PMOS channel, using the insulating material layer as a mask. The method does not require the use of multiple masks that may cause misalignment in the channel regions.

Abstract: The invention provides a method for forming a transistor, which includes: providing a substrate, a semiconductor layer being formed on the substrate; forming a dummy gate structure on the semiconductor layer; forming a source region and a drain region in the substrate and the semiconductor layer and at opposite sides of the dummy gate structure; forming an interlayer dielectric layer on the semiconductor layer; removing the dummy gate structure for forming an opening in the interlayer dielectric layer; non-crystallizing the semiconductor layer exposed in the opening for forming a channel layer; annealing the channel layer so that the channel layer and the substrate have same crystal orientation; and forming a metal gate structure in the opening, the metal gate being formed on the channel layer. Saturation current of the transistor is raised, and the performance of a semiconductor device is promoted.

Abstract: A device having thin-film transistor (TFT) floating gate memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N+ polysilicon layer on a diffusion barrier layer which is on a first conductive layer. The N+ polysilicon layer has a second surface substantially co-planar with the first surface. Additionally, the device includes a P? polysilicon layer overlying the co-planar surface and a floating gate on the P? polysilicon layer. The floating gate is a low-pressure CVD-deposited silicon layer sandwiched by a bottom oxide tunnel layer and an upper oxide block layer. Moreover, the device includes at least one control gate made of a P+ polysilicon layer overlying the upper oxide block layer.

Abstract: A method of growing an epitaxial silicon layer is provided. The method comprising providing a substrate including an oxygen-terminated silicon surface and forming a first hydrogen-terminated silicon surface on the oxygen-terminated silicon surface. Additionally, the method includes forming a second hydrogen-terminated silicon surface on the first hydrogen-terminated silicon surface through atomic-layer deposition (ALD) epitaxy from SiH4 thermal cracking radical assisted by Ar flow and flash lamp annealing continuously. The second hydrogen-terminated silicon surface is capable of being added one or more layer of silicon through ALD epitaxy from SiH4 thermal cracking radical assisted by Ar flow and flash lamp annealing continuously. In one embodiment, the method is applied for making devices with thin-film transistor (TFT) floating gate memory cell structures which is capable for three-dimensional integration.

Abstract: The invention provides a phase change memory and a method for forming the phase change memory. The phase change memory includes a storage region and a peripheral circuit region. The peripheral circuit region has a peripheral substrate, peripheral shallow trench isolation (STI) units in the peripheral substrate, and MOS transistors on the peripheral substrate and between the peripheral STI units. The storage region has a storage substrate, an N-type ion buried layer on the storage substrate, vertical LEDs on the on the N-type ion buried layer, storage shallow trench isolation (STI) units between the vertical LEDs, and phase change layers on the vertical LEDs and between the storage STI units. The storage STI units have thickness equal to thickness of the vertical LEDs. Each vertical LED comprises an N-type conductive region on the N-type ion buried layer, and a P-type conductive region on the N-type conductive region. The P-type conductive region contains SiGe.

Abstract: The present invention relates to a semiconductor device and its manufacturing method. The semiconductor device comprises: a gate structure located on a substrate, Ge-containing semiconductor layers located on the opposite sides of the gate structure, a doped semiconductor layer epitaxially grown between the Ge-containing semiconductor layers, the bottom surfaces of the Ge-containing semiconductor layers located on the same horizontal plane as that of the epitaxial semiconductor layer. The epitaxial semiconductor layer is used as a channel region, and the Ge-containing semiconductor layers are used as source/drain extension regions.

Abstract: This disclosure relates to a semiconductor device and a manufacturing method thereof. The semiconductor device comprises: a patterned stacked structure formed on a semiconductor substrate, the stacked structure comprising a silicon-containing semiconductor layer overlaying the semiconductor substrate, a gate dielectric layer overlaying the silicon-containing semiconductor layer and a gate layer overlaying the gate dielectric layer; and a doped epitaxial semiconductor layer on opposing sides of the silicon-containing semiconductor layer forming raised source/drain extension regions. Optionally, the silicon-containing semiconductor layer may be used as a channel region. According to this disclosure, the source/drain extension regions can be advantageously made to have a shallow junction depth (or a small thickness) and a high doping concentration.

Abstract: A method for fabricating semiconductor devices includes providing a semiconductor substrate having a surface region containing one or more contaminants and having an overlying oxide layer. In an embodiment, the one or more contaminants are at least a carbon species. The method includes processing the surface region using at least a wet processing process to selectively remove the overlying oxide layer and expose the surface region including the one or more contaminants. The method includes subjecting the surface region to a high energy electromagnetic radiation having wavelengths ranging from about 300 to about 800 nanometers for a time period of less than 1 second to increase a temperature of the surface region to greater than 1000 degrees Celsius to remove the one or more contaminants. The method includes removing the high energy electromagnetic radiation to cause a reduction in temperature to about 300 to about 600 degrees Celsius in a time period of less than 1 second.

Abstract: Disclosed are atomic layer deposition method and a semiconductor device including the atomic layer, including the steps: placing a semiconductor substrate in an atomic layer deposition chamber; feeding a first precursor gas to the semiconductor substrate within the chamber to form a first discrete monolayer on the semiconductor substrate; feeding an inert purge gas to the semiconductor substrate within the chamber to remove the first precursor gas which has not formed the first discrete monolayer on the semiconductor substrate; feeding a second precursor gas to the chamber to react with the first precursor gas which has formed the first discrete monolayer, forming a discrete atomic size islands; and feeding an inert purge gas to the semiconductor substrate within the chamber to remove the second precursor gas which has not reacted with the first precursor gas and byproducts produced by the reaction between the first and the second precursor gases.

Abstract: A semiconductor non-volatile memory (NVM) device, comprising: a semiconductor substrate; a three-layer stack structure of medium layer-charge trapping layer-medium layer disposed on the semiconductor substrate; a gate disposed above the three-layer stack structure; a source and a drain disposed in the semiconductor substrate at either side of the three-layer stack structure; wherein the charge trapping layer is a dielectric layer containing one or more discrete compound clusters formed by atomic layer deposition (ALD) method.