Patents by Inventor Fumitake Mieno

Fumitake Mieno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5233163
    Abstract: A heating apparatus for use in heating a substrate comprises an electric heater and a power supply part. The electric heater is made up of an approximately columnar body which is made of graphite, and this columnar body has a top with a flat surface part on which the substrate is placed and a pair of legs which extend downwardly from the flat surface part. The legs are defined by an opening in the columnar body. The power supplying part is coupled to the electric heater and supplies a voltage across the legs of the columnar body so that a current flows from one leg to the other, thereby generating heat at the flat surface part to heat the substrate.
    Type: Grant
    Filed: July 3, 1991
    Date of Patent: August 3, 1993
    Assignee: Fujitsu Limited
    Inventors: Fumitake Mieno, Yuji Furumura, Atsuhiro Tsukune, Hiroshi Miyata
  • Patent number: 5111266
    Abstract: A bipolar transistor includes a base region made of silicon crystal doped with a first impurity to a first level so as to establish a first carrier concentration in the base region and an emitter region made of silicon crystal doped with a second impurity to a second level substantially larger than the first level by a predetermined factor so as to establish a second carrier concentration in the emitter region, in which the second impurity exceeds the solubility limit of the second impurity in silicon crystal. The first and second levels are chosen in such a range that a difference in the carrier concentrations between the emitter region and the base region decreases substantially with increasing impurity level in the base region.
    Type: Grant
    Filed: June 12, 1991
    Date of Patent: May 5, 1992
    Assignee: Fujitsu Limited
    Inventors: Yuji Furumura, Fumitake Mieno, Tsutomu Nakazawa, Takashi Eshita, Mamoru Maeda, Tsunenori Yamauchi
  • Patent number: 5103285
    Abstract: A silicon carbide layer between a silicon substrate or layer and a metal layer because silicon carbide has many properties similar to those of silicon, has a very slow diffusion rate of a metal through the silicon carbide, or prevents a diffusion of a metal into the silicon, and can be deposited by CVD, which has an advantage of a good coverage over a step portion such as a contact window.
    Type: Grant
    Filed: December 19, 1988
    Date of Patent: April 7, 1992
    Assignee: Fujitsu Limited
    Inventors: Yuji Furumura, Fumitake Mieno, Takashi Eshita, Kikuo Itoh, Masahiko Doki
  • Patent number: 5082695
    Abstract: A method of fabricating an X-ray exposure mask including the steps of forming a .beta.-SiC membrane by chemcial vapor deposition and simultaneously doping the membrane with at least one of phosphorous, boron, nitrogen and oxygen.
    Type: Grant
    Filed: February 24, 1989
    Date of Patent: January 21, 1992
    Assignee: 501 Fujitsu Limited
    Inventors: Masao Yamada, Masafumi Nakaishi, Kenji Nakagawa, Yuji Furumura, Takashi Eshita, Fumitake Mieno
  • Patent number: 4966861
    Abstract: A method for simultaneously forming an epitaxial silicon layer on a surface of a silicon substrate, and a polysilicon layer on a silicon dioxide (SiO.sub.2) layer which is formed on the silicon substrate using a low pressure silicon vapor deposition method, employing silicon hydride gas, particularly disilane (Si.sub.2 O.sub.6), as a silicon source gas. A crystal growing temperature ranging from 780.degree. C. to 950.degree. C. and a reaction gas pressure ranging from 20 Torr to 300 Torr are desirable. An extended silicon epitaxial region is achieved under a higher temperature and a higher gas pressure, and with a substrate of a (100) orientation. A polysilicon layer having an even surface and joining smoothly to an epitaxial silicon layer which is simultaneously formed, is obtained under a lower temperature and a lower gas pressure, and with a substrate of a (111) orientation.
    Type: Grant
    Filed: April 25, 1989
    Date of Patent: October 30, 1990
    Assignee: Fujitsu Limited
    Inventors: Fumitake Mieno, Kazuyuki Kurita, Shinji Nakamura, Atuo Shimizu
  • Patent number: 4879255
    Abstract: The present invention is a method for fabricating bipolar-MOS devices having n-MOSs, p-MOSs and bipolar transistors, each fabricated in a respective silicon single crystal layer grown in openings formed in a field oxide layer covering a silicon substrate. Over the field oxide layer, having openings where the active devices should be fabricated, is applied an epitaxial growth of silicon. By this operation, single crystal layers are formed in the openings, and a polysilicon layer is formed on the field oxide layer. The polysilicon layer is patterned to form the source and drain contact electrodes of the FETs and the base and collector contact electrodes of the bipolar transistors simultaneously. To the active areas, contact electrodes for the p-MOS, and base contact electrodes of the npn bipolar transistors are simultaneously implanted with p type impurities by ion implantation.
    Type: Grant
    Filed: June 1, 1988
    Date of Patent: November 7, 1989
    Assignee: Fujitsu Limited
    Inventors: Tatsuya Deguchi, Fumitake Mieno
  • Patent number: 4876219
    Abstract: A method of forming a semiconductor thin layer on a silicon substrate comprising the steps of depositing a first amorphous layer of a compound semiconductor (e.g., GaAs) on the silicon substrate, and growing a first epitaxial layer of the compound semiconductor on the amorphous layer, characterized in that the method comprises the steps of: after the epitaxial growth step, depositing a second amorphous layer of the compound semiconductor on the first epitaxial layer, and growing a second epitaxial layer of the compound semiconductor on the second amorphous layer. The obtained GaAs/Si substrate has a reduced dislocation density.
    Type: Grant
    Filed: March 3, 1989
    Date of Patent: October 24, 1989
    Assignee: Fujitsu Limited
    Inventors: Takashi Eshita, Fumitake Mieno, Yuji Furumura, Takuya Watanabe
  • Patent number: 4855254
    Abstract: A single crystalline silicon carbide (.beta.-SiC) layer having a thickness greater than 1 .mu.m is grown on a silicon substrate by the following method of the present invention. The silicon substrate is provided in a reactor chamber, and the reactor chamber is evacuated and maintained at a reduced atmospheric pressure during the growing processes. While flowing a mixed gas containing acetylene into the reactor chamber, the substrate is heated up at a temperature range from 800.degree. to 1000.degree. C., preferable in a range from 810.degree. to 850.degree. C., whereby a buffer layer of carbonized silicon having a thickness of 60 to 100 .ANG. is grown on the substrate. Thereafter, the flowing gas is changed to a mixed gas containing hydrocarbon and chlorosilane, and the substrate temperature is raised to a temperature from 850.degree. to 950.degree. C. In this process, a single crystalline .beta.-SiC layer can be grown on the buffer layer, and a thickness of a few .mu.m for the grown .beta.
    Type: Grant
    Filed: December 13, 1988
    Date of Patent: August 8, 1989
    Assignee: Fujitsu Limited
    Inventors: Takashi Eshita, Fumitake Mieno, Yuji Furumura, Kikuo Itoh
  • Patent number: 4825809
    Abstract: A chemical vapor deposition apparatus for ejecting reaction gas over an object on which a layer of the reaction gas is to be deposited has an ejecting head which develops a uniformly distributed laminated flow of the reaction gas along its inner surface. The ejecting head is formed from an inverted conical housing portion and a circular perforated plate covering the open end thereof. An ejecting member protrudes into a top end of the head and ejects the gas into the space inside the head in predetermined directions. The housing encloses the ejecting member and directs the gas ejected from the ejecting member to flow downward along the inner surface thereof in a laminated state. The laminated flow of gas continues onto the perforated plate, on which it flows centripetally along the inner surface thereof, being ejected evenly downward from the plate through holes in the plate.
    Type: Grant
    Filed: March 3, 1988
    Date of Patent: May 2, 1989
    Assignee: Fujitsu Limited
    Inventor: Fumitake Mieno
  • Patent number: 4804560
    Abstract: A method of selectively depositing tungsten upon a silicon semiconductor substrate. A silicon substrate is coated with a masking film of PSG or SiO.sub.2 that is patterned to provide an opening for forming an electrode or wiring. On a portion of the substrate in the opening, a layer of tungsten having a thickness of approximately 2000 .ANG. is deposited by a CVD method from an atomosphere containing a gaseous mixture of WF.sub.6 and H.sub.2 . During this processing, tungsten nucleuses deposit on the surface of the masking film as well. Before such nucleuses form a film, the deposition processing is discontinued and H.sub.2 gas is fed into the CVD apparatus to produce HF, which etches the surface of the masking film, and thus tungsten nucleuses are removed. The deposition and removal steps are repeated several times until the height of the deposited tungsten and the thickness of the masking film are essentially equal to present a flat surface.
    Type: Grant
    Filed: March 17, 1987
    Date of Patent: February 14, 1989
    Assignee: Fujitsu Limited
    Inventors: Yoshimi Shioya, Yasushi Oyama, Norihisa Tsuzuki, Mamoru Maeda, Masaaki Ichikawa, Fumitake Mieno, Shin-ichi Inoue, Yasuo Uo-ochi, Akira Tabuchi, Atsuhiro Tsukune, Takuya Watanabe, Takayuki Ohba