Patents by Inventor Fumitomo Watanabe

Fumitomo Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8710647
    Abstract: A semiconductor device includes a wiring board having connection pads thereon and a semiconductor chip mounted on the wiring board. The wiring board and the semiconductor chip are covered with a sealing portion. Conductive members are extended upward from the connection pads and are exposed from the sealing portion. Rewiring lines are connected to the exposed conductive members. Land portions are arranged on the sealing portion and are electrically connected to the conductive members through the rewiring lines.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: April 29, 2014
    Inventors: Yutaka Kagaya, Fumitomo Watanabe, Hajime Takasaki
  • Publication number: 20140035161
    Abstract: A semiconductor device includes a first wiring board, a second semiconductor chip, and a second seal. The first wiring board includes a first substrate, a first semiconductor chip, and a first seal. The first semiconductor chip is disposed on the first substrate. The first seal is disposed on the first substrate. The first seal surrounds the first semiconductor chip. The first seal has the same thickness as the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip. The first semiconductor chip is between the second semiconductor chip and the first substrate. The second semiconductor chip is greater in size in plan view than the first semiconductor chip. The second seal seals at least a first gap between the first semiconductor chip and the second semiconductor chip.
    Type: Application
    Filed: October 10, 2013
    Publication date: February 6, 2014
    Applicant: Elpida Memory, Inc.
    Inventors: Masanori YOSHIDA, Fumitomo Watanabe
  • Patent number: 8575763
    Abstract: A semiconductor device includes a first wiring hoard, a second semiconductor chip, and a second seal. The first wiring board includes a first substrate, a first semiconductor chip, and a first seal. The first semiconductor chip is disposed on the first substrate. The first seal is disposed on the first substrate. The first seal surrounds the first semiconductor chip. The first seal has the same thickness as the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip. The first semiconductor chip is between the second semiconductor chip and the first substrate. The second semiconductor chip is greater in size in plan view than the first semiconductor chip. The second seal seals at least a first gap between the first semiconductor chip and the second semiconductor chip.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: November 5, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Masanori Yoshida, Fumitomo Watanabe
  • Publication number: 20120032353
    Abstract: A semiconductor device includes a wiring board having connection pads thereon and a semiconductor chip mounted on the wiring board. The wiring board and the semiconductor chip are covered with a sealing portion. Conductive members are extended upward from the connection pads and are exposed from the sealing portion. Rewiring lines are connected to the exposed conductive members. Land portions are arranged on the sealing portion and are electrically connected to the conductive members through the rewiring lines.
    Type: Application
    Filed: October 17, 2011
    Publication date: February 9, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Yutaka KAGAYA, Fumitomo WATANABE, Hajime TAKASAKI
  • Patent number: 8076770
    Abstract: A semiconductor device includes a wiring board having connection pads thereon and a semiconductor chip mounted on the wiring board. The wiring board and the semiconductor chip are covered with a sealing portion. Conductive members are extended upward from the connection pads and are exposed from the sealing portion. Rewiring lines are connected to the exposed conductive members. Land portions are arranged on the sealing portion and are electrically connected to the conductive members through the rewiring lines.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: December 13, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Yutaka Kagaya, Fumitomo Watanabe, Hajime Takasaki
  • Patent number: 7993975
    Abstract: A semiconductor-device manufacturing method includes: forming terminals on a wafer and across each of dicing lines along which the wafer is cut into a plurality of semiconductor chips; preparing a plurality of pre-cut substrates each including a substrate body capable of being cut along corresponding one of cutting lines into a pair of same structured substrate pieces, connection pads provided on a top surface of the substrate body, and external terminals formed on a bottom surface of the substrate body and connected to the connection pads; mounting the pre-cut substrates onto the wafer while the cutting lines of the pre-cut substrates match the dicing lines; and simultaneously dicing the wafer and the pre-cut substrates along the dicing lines matching the cutting lines.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: August 9, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Mitsuhisa Watanabe, Fumitomo Watanabe
  • Patent number: 7928551
    Abstract: In a semiconductor device, a first semiconductor chip is stacked on a wiring substrate and has first electrode pads disposed at predetermined positions on an upper surface thereof. A second semiconductor chip is stacked on the first semiconductor chip through an insulating member in an offset manner so that the first electrode pads are exposed. Support members support a back surface of a protruding portion of the second semiconductor chip through the insulating member.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: April 19, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Reiko Fujiwara, Akihiko Hatasawa, Fumitomo Watanabe
  • Publication number: 20110057327
    Abstract: A semiconductor device includes a first wiring hoard, a second semiconductor chip, and a second seal. The first wiring board includes a first substrate, a first semiconductor chip, and a first seal. The first semiconductor chip is disposed on the first substrate. The first seal is disposed on the first substrate. The first seal surrounds the first semiconductor chip. The first seal has the same thickness as the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip. The first semiconductor chip is between the second semiconductor chip and the first substrate. The second semiconductor chip is greater in size in plan view than the first semiconductor chip. The second seal seals at least a first gap between the first semiconductor chip and the second semiconductor chip.
    Type: Application
    Filed: September 9, 2010
    Publication date: March 10, 2011
    Inventors: Masanori YOSHIDA, Fumitomo Watanabe
  • Patent number: 7888179
    Abstract: The semiconductor device is made up of two wiring boards, a semiconductor chip, and a sealing part. The two wiring boards are spaced apart, and a semiconductor chip is mounted so as to span the two wiring boards. The semiconductor chip includes a predetermined circuit and a plurality of electrode pads on one side thereof. The wiring board includes a plurality of connection pads on a semiconductor chip-mounting face, and a plurality of lands on the opposite side thereof. The land is electrically connected to a corresponding connection pad. An external terminal is formed on each of the lands. Further, the electrode pad formed in the semiconductor chip is electrically connected to the corresponding connection pad of the wiring board. Moreover, the semiconductor chip, the semiconductor chip mounting face of the wiring board, and the side faces of the wiring board are covered with the sealing part.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: February 15, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Yutaka Kagaya, Fumitomo Watanabe
  • Publication number: 20100102438
    Abstract: A semiconductor device includes: a substrate having first and second surfaces, the first surface comprising first and second regions; a first semiconductor chip covering the first region; a first seal covering the second region and the first semiconductor chip; and a second seal covering the second surface.
    Type: Application
    Filed: October 13, 2009
    Publication date: April 29, 2010
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Mitsuhisa Watanabe, Fumitomo Watanabe
  • Publication number: 20090321920
    Abstract: A semiconductor device includes: a substrate; a plurality of connection pads provided on the substrate; a semiconductor chip; a plurality of electrode pads provided on the semiconductor chip; a plurality of wires electrically connecting the connection pads and the electrode pads; and a seal covering the semiconductor chip and the wires. The semiconductor chip is distanced from the substrate while being placed inside a periphery of the substrate. The seal intervenes between the semiconductor chip and the substrate.
    Type: Application
    Filed: June 12, 2009
    Publication date: December 31, 2009
    Applicant: Elpida Memory, Inc.
    Inventors: Shinichi Sakurada, Fumitomo Watanabe
  • Publication number: 20090189297
    Abstract: To provide a semiconductor device having high reliability by reducing the bending of a semiconductor device and mitigating stress exerted on external terminals. In a semiconductor device 1 having a semiconductor chip 9 mounted on a wiring substrate 2 comprising a base member 3 having a predetermined conductive pattern formed on both surfaces, slits 8 that penetrate the base member 3 in the vertical direction of the base member 3 are provided. When the semiconductor chip 9 and a wire 12 are sealed with resin, the same resin is used to fill the slits 8.
    Type: Application
    Filed: January 27, 2009
    Publication date: July 30, 2009
    Inventors: Katsumi Sugawara, Fumitomo Watanabe
  • Publication number: 20090166863
    Abstract: A semiconductor-device manufacturing method includes: forming terminals on a wafer and across each of dicing lines along which the wafer is cut into a plurality of semiconductor chips; preparing a plurality of pre-cut substrates each including a substrate body capable of being cut along corresponding one of cutting lines into a pair of same structured substrate pieces, connection pads provided on a top surface of the substrate body, and external terminals formed on a bottom surface of the substrate body and connected to the connection pads; mounting the pre-cut substrates onto the wafer while the cutting lines of the pre-cut substrates match the dicing lines; and simultaneously dicing the wafer and the pre-cut substrates along the dicing lines matching the cutting lines.
    Type: Application
    Filed: December 18, 2008
    Publication date: July 2, 2009
    Inventors: Mitsuhisa Watanabe, Fumitomo Watanabe
  • Publication number: 20090129036
    Abstract: A semiconductor device includes: a wiring substrate that includes multiple connection pads provided on a top surface thereof and multiple lands provided on a bottom surface thereof and electrically connected to the connection pads, respectively; a semiconductor chip that is mounted on the top surface of the wiring substrate; multiple electrode pads provided on the semiconductor chip; wirings that electrically connect the electrode pads and the connection pads, respectively; a seal that is made of an insulating resin and covers at least the semiconductor chip and the wirings; and a through hole that is provided on a peripheral region of the wiring substrate, into which a fixing member is to be attached by insertion
    Type: Application
    Filed: November 13, 2008
    Publication date: May 21, 2009
    Applicant: ELPIDA MEMORY, INC.
    Inventors: SEIYA FUJII, Fumitomo Watanabe
  • Publication number: 20090096111
    Abstract: In a semiconductor device, a first semiconductor chip is stacked on a wiring substrate and has first electrode pads disposed at predetermined positions on an upper surface thereof. A second semiconductor chip is stacked on the first semiconductor chip through an insulating member in an offset manner so that the first electrode pads are exposed. Support members support a back surface of a protruding portion of the second semiconductor chip through the insulating member.
    Type: Application
    Filed: October 15, 2008
    Publication date: April 16, 2009
    Applicant: Elpida Memory, Inc.
    Inventors: Reiko Fujiwara, Akihiko Hatasawa, Fumitomo Watanabe
  • Publication number: 20090045497
    Abstract: A semiconductor device includes a wiring board having connection pads thereon and a semiconductor chip mounted on the wiring board. The wiring board and the semiconductor chip are covered with a sealing portion. Conductive members are extended upward from the connection pads and are exposed from the sealing portion. Rewiring lines are connected to the exposed conductive members. Land portions are arranged on the sealing portion and are electrically connected to the conductive members through the rewiring lines.
    Type: Application
    Filed: August 12, 2008
    Publication date: February 19, 2009
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Yutaka KAGAYA, Fumitomo WATANABE, Hajime TAKASAKI
  • Publication number: 20090039506
    Abstract: The semiconductor device is made up of two wiring boards, a semiconductor chip, and a sealing part. The two wiring boards are spaced apart, and a semiconductor chip is mounted so as to span the two wiring boards. The semiconductor chip includes a predetermined circuit and a plurality of electrode pads on one side thereof. The wiring board includes a plurality of connection pads on a semiconductor chip-mounting face, and a plurality of lands on the opposite side thereof. The land is electrically connected to a corresponding connection pad. An external terminal is formed on each of the lands. Further, the electrode pad formed in the semiconductor chip is electrically connected to the corresponding connection pad of the wiring board. Moreover, the semiconductor chip, the semiconductor chip mounting face of the wiring board, and the side faces of the wiring board are covered with the sealing part.
    Type: Application
    Filed: August 5, 2008
    Publication date: February 12, 2009
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Yutaka Kagaya, Fumitomo Watanabe