Abstract: A liquid chromatograph includes: a liquid meter that measures a liquid amount of a mobile phase stored in one or more mobile phase containers; and a notification unit that notifies an operator of the liquid amount of the mobile phase in each of the one or more mobile phase containers measured by the liquid meter. According to such a liquid chromatograph, when the operator replenishes the mobile phase to the mobile phase container, it is not necessary to visually measure the liquid amount of the mobile phase or manually input the value to the control device, so that it is possible to reduce the workload of the operator regarding the liquid amount management of the mobile phase.

Abstract: The automatic suitability determination system includes a check document storing part, a check document retrieving part, a determination test execution part, and a suitability determination part. The check document storing part stores suitability check documents. The check document retrieving part is configured to read out the suitability check document related to a determining target component of operational suitability from the check document storing part. The determination test execution part is configured to read information contained in the suitability check document read out by the check document retrieving part and to execute tests of suitability determination items specified in the suitability check document by making the determining target component of the operational suitability operate based on the information.

Abstract: Analysis control software is installed in an analysis control device. The analysis control software is the software for controlling an analysis device, and has a function of causing a display to display one or a plurality of operation images for receiving an operation for inspecting the analysis control software. In a validation device, operation commands for performing an operation on one or a plurality of operation images are sequentially generated by an inspection executor with the one or plurality of operation images displayed in the display, whereby an inspection is executed by the analysis control software.

Abstract: A controlling apparatus 110 to control an operation of an analyzing apparatus 1 and make the analyzing apparatus 1 execute a predetermined analysis, the controlling apparatus 110 including: a communicating module 60 that maintains reception of electricity when the analyzing apparatus 1 is in a power-on state, and is capable of receiving a control signal from an external apparatus 2 at all times; and a unit power controlling section 23 for acquiring the control signal through the communicating module 60, stopping electricity supply to a unit 31, 321, 322, 323 and/or 324 of the analyzing apparatus 1 at a first timing based on the control signal, and restarting the electricity supply to the unit 31, 321, 322, 323 and/or 324 at a second timing based on the control signal, so as to effectively suppress the electricity consumption when the analysis is not executed and facilitate the restart of the analysis.

Abstract: A controlling apparatus controls an operation of an analyzing apparatus and makes the analyzing apparatus execute a predetermined analysis. The controlling apparatus includes a communicating module that maintains reception of electricity when the analyzing apparatus is in a power-on state, and is capable of receiving a control signal from an external apparatus at all times; and unit power controlling means for acquiring the control signal through the communicating module, stopping electricity supply to a unit of the analyzing apparatus at a first timing based on the control signal, and restarting the electricity supply to the unit at a second timing based on the control signal, so as to effectively suppress the electricity consumption when the analysis is not executed and facilitate the restart of the analysis.

Abstract: A semiconductor device includes a semiconductor wafer in which semiconductor chip forming regions and a scribe region located between the semiconductor chip forming regions are formed, a plurality of semiconductor chip circuit portions provided over the semiconductor wafer, a plurality of first conductive layers, provided in each of the semiconductor chip forming regions, which is electrically connected to each of the circuit portions, and a first connecting portion that electrically connects the first conductive layers to each other across a portion of the scribe region. An external power supply or grounding pad is connected to any one of the first conductive layer and the first connecting portion. The semiconductor device includes a communication portion, connected to the circuit portion, which performs communication with the outside by capacitive coupling or inductive coupling.

Abstract: A semiconductor device includes a semiconductor wafer in which semiconductor chip forming regions and a scribe region located between the semiconductor chip forming regions are formed, a plurality of semiconductor chip circuit portions provided over the semiconductor wafer, a plurality of first conductive layers, provided in each of the semiconductor chip forming regions, which is electrically connected to each of the circuit portions, and a first connecting portion that electrically connects the first conductive layers to each other across a portion of the scribe region. An external power supply or grounding pad is connected to any one of the first conductive layer and the first connecting portion. The semiconductor device includes a communication portion, connected to the circuit portion, which performs communication with the outside by capacitive coupling or inductive coupling.

Abstract: From power supply potential wiring to ground potential wiring, a first inductor, a first resistance, a first output terminal, and a first transistor are series-connected in this order, and in parallel with these, a second inductor, a second resistor, a second output terminal, and a second transistor are series-connected in this order. And, one electrode of a first variable capacitor is connected between the first inductor and first resistor, and one electrode of a second variable capacitor is connected between the second inductor and second resistor. The other electrodes of the first variable capacitor and second variable capacitor are connected to a first frequency characteristics control terminal and a second frequency characteristics control terminal, respectively.

Abstract: At the same control voltage Vtune, the oscillation frequency with only switches SW3 and SW4 being closed is higher than that with only switches SW1 and SW2 being closed. Accordingly, even when the oscillation frequency is lower than designed with only the switches SW1 and SW2 being closed and the capacitance of varactor diodes D1 and D2 cannot be controlled to provide the desired oscillation frequency, the desired oscillation frequency can be provided by closing only the switches SW3 and SW4 to control the capacitance of the varactor diodes D1 and D2. On the oscillation frequency, a coarse tuning can be performed by controlling the switches SW1 to SW4, while a fine tuning can be performed with the varactor diodes D1 and D2. Consequently, the range of the oscillation frequency is increased.

Abstract: An LC circuit including an inductor and a pair of varactor elements is provided in an LC-VCO. This LC circuit outputs complementary alternating current signals from a pair of output terminals. The varactor element is formed by providing a gate electrode on an N well. Then, the well terminals of the varactor elements are connected to the respective output terminals, and the gate terminals of the varactor elements are connected to a control terminal. Thereby, as a control voltage to be applied to the control terminal becomes higher, the capacitance of the varactor element increases, and the frequency of the alternating current signal lowers.

Abstract: A solid-state imaging device has an array of pixels arranged in a matrix pattern of rows and columns. Each pixel has a photodiode for developing a voltage corresponding to light incident thereon, a first amplifying transistor for amplifying the voltage and a row select switching transistor responsive to a row select signal from a row line for coupling the amplified voltage to a column line. Multiple second amplifying transistors are respectively connected to multiple column lines. When the row select switching transistors of the pixels in one of the rows are turned on in response to a row select signal, the second amplifying transistors and the first amplifying transistors of the selected row jointly constitute voltage followers for respectively amplifying the voltages coupled to the column lines. Multiple column select switching transistors provide sequentially coupling of the outputs of the voltage followers to an output line in response to column select signals.

Abstract: From power supply potential wiring to ground potential wiring, a first inductor, a first resistance, a first output terminal, and a first transistor are series-connected in this order, and in parallel with these, a second inductor, a second resistor, a second output terminal, and a second transistor are series-connected in this order. And, one electrode of a first variable capacitor is connected between the first inductor and first resistor, and one electrode of a second variable capacitor is connected between the second. inductor and second resistor. The other electrodes of the first variable capacitor and second variable capacitor are connected to a first frequency characteristics control terminal and a second frequency characteristics control terminal, respectively.

Abstract: A hierarchical readout circuit includes a plurality of first capacitors for respectively interposed in a plurality of lines at which individual voltages are developed. Before the individual voltages appear at the lines, the inputs of the first capacitors are simultaneously biased at least once, and the outputs of the first capacitors are simultaneously biased. The output of each of the first capacitors is selectively biased again in the presence of the individual voltages at the lines. A plurality of buffers are connected in stages in a hierarchical configuration to the outputs of the first capacitors. Scanning circuitry selectively couples the output of a lower-stage buffer to a higher-stage buffer via a second capacitor. The output of the second capacitor is first biased before the individual voltages appear at the lines and then at periodic intervals before each first capacitor is selectively biased again.

Abstract: At the same control voltage Vtune, the oscillation frequency with only switches SW3 and SW4 being closed is higher than that with only switches SW1 and SW2 being closed. Accordingly, even when the oscillation frequency is lower than designed with only the switches SW1 and SW2 being closed and the capacitance of varactor diodes D1 and D2 cannot be controlled to provide the desired oscillation frequency, the desired oscillation frequency can be provided by closing only the switches SW3 and SW4 to control the capacitance of the varactor diodes D1 and D2. On the oscillation frequency, a coarse tuning can be performed by controlling the switches SW1 to SW4, while a fine tuning can be performed with the varactor diodes D1 and D2. Consequently, the range of the oscillation frequency is increased.

Abstract: The solid state imaging device comprising active pixels has a structure in which transistors for amplification 103 and 113 which amplify an output signal of a photodiode 101 composing a photoelectric conversion portion are constituted as a voltage follower. By using the transistors for amplification 103 and 113 having a voltage follower structure, a gain of amplifying a signal from each pixel is made unity, and an amplification gain can be larger than that of an amplification circuit having a conventional source follower structure. Thereby, noise immunity is improved. Also, by inserting switching transistors corresponding to row selecting transistors, circuit symmetry of a differential amplifier circuit can be improved.

Abstract: There is provided a solid-state image sensor including (a) a plurality of pixels arranged in a matrix in a photoelectric transfer region, (b) at least one movement-detector located in the photoelectric transfer region, (c) a first Y-scanner making successive access to the pixels in rows in a predetermined region in the photoelectric transfer region, and (d) a first X-scanner reading out signals running through signal output lines extending through the predetermined region. The first and second scanners both scan a predetermined region associated with a movement-detector which has transmitted a detection signal. The solid-state image sensor makes it possible to immediately detect movement when it has occurred, identify a region in which movement has occurred, and detect movement while carrying out scanning in a normal mode.

Abstract: The present invention provides a solid-state image pick-up device which is capable of displaying its image pick-up ability more than that of the related art. A sensor array is composed of photoelectric conversion cells arranged in the form of a matrix. An X scanner and a Y scanner scan the respective photoelectric conversion cells. A VGA amplifies output voltages of the respective photoelectric conversion cells, and an ADC converts an output voltage of the VGA into digital data. An average computing unit computes the average value of output voltages of the respective photoelectric conversion cells in a predetermined area of the sensor array on the basis of the output of the ADC. A divider divides a reference value by the average value and outputs the result of division to a multiplier.

Abstract: A photoreceiver circuit includes (a) a photoelectric conversion element for converting incident light to a current, (b) an analog voltage amplifier circuit for amplifying a voltage corresponding to the current of the photoelectric conversion element and for producing an amplified voltage as an output of the photoreceiver circuit, and (c) an analog multiplier circuit for multiplying the amplified voltage produced by the voltage amplifier circuit by an adjusting voltage and for producing an output current with a component proportional to a product of the amplified voltage and the adjusting voltage. The output current of the analog multiplier circuit is supplied to the photoelectric converter element, thereby forming a feedback path of the voltage amplifier circuit. A voltage-lowering part and a current-leaking part may be additionally provided.

Abstract: A latch circuit with an NAND function comprises a three-input NAND gate circuit, a first transfer gate connected between a first input terminal and a first input of the NAND gate circuit, a second transfer gate connected between a second input terminal and a second input of the NAND gate circuit, and a third transfer gate connected between a third input terminal and a third input of the NAND gate circuit. An input of a feedback inverter is connected To an output of the NAND gate circuit, and an output of the feedback inverter is connected to the first input of the NAND gate circuit through a fourth transfer gate. The second and third inputs of the NAND gate circuit are pulled up to a logical high level through P-channel MOS transistors.

Abstract: A priority encoder for a normalization at a floating-point addition of subtraction for encoding a leading zero number of a difference of two input binary numbers within an error of -1, and a floating-point adder-subtractor using this priority encoder. The priority encoder includes a pre-encoder for outputting an n-bit bit string Q (=Q.sub.n, Q.sub.n-1, . . . and Q.sub.1,) from a combination (X.sub.i, Y.sub.i, X.sub.i-1, Y.sub.i-1) of ith and (i-1)th digits of input two binary numbers X and Y, and a conventional priority encoder circuit for encoding the bit string Q output from the pre-encoder. The floating-point adder-subtractor includes the priority encoder operating in parallel with a mantissa add-subtract circuit so as to output the leading zero number of the difference between the two binary numbers X and Y.