Abstract: Apparatus for use in a floating-point and fixed-point adder-subtractor assembly. The apparatus includes a comparator and selector circuit disposed prior to an adder-subtracter for determining a larger and smaller operand prior to the addition and subtraction operation. The comparator and selector circuit inputs the larger operand into a first predetermined input of the adder-subtracter and the smaller operand into a second predetermined input of the adder-subtracter. Additionally, first and second selector circuits may be provided for multiplexing first and second fixed point data operands into the first and second inputs of the adder-subtracter, respectively. A shifter is provided for shifting at least one of the operands prior to inputting the operand into the adder-subtracter for selectively performing a position alignment. Accordingly, a simplified structure provides fixed-point and floating-point data addition-subtraction in a highly efficient manner.

Abstract: In vector dividing the process employing convergence division method, the process steps are performed for performing pipeline processing of multiplying operation of the dividend and a first convergence factor in a speed of one clock cycle per one element to generate a first intermediate result vector data as a data before convergence, for performing pipeline processing of multiplying operation of the divisor and the first convergence factor in a speed of one clock cycle per one element to generate a second intermediate result vector data as a data before convergence, for storing the first and second intermediate result vector data to first and second intermediate result storing vector registers, respectively, for reading out of the first and second intermediate result vector data from the first and second intermediate result storing vector registers, respectively, per every clock cycles, for performing pipeline processing for multiplying operation of the read out intermediate result vector data and a second c

Abstract: In a floating point arithmetic addition/subtraction system which is configured to receive a pair of input operands of floating point data including its mantissa part expressed in an absolute value so as to execute an addition/subtraction and which includes a mantissa adder, a normalizing shifter, an exponent part updater and a bit position decoder, integer data expressed in a 2's complement is supplied as one of the pair of input operands, and the integer data is converted into an absolute value by using the mantissa adder. Thereafter, the bit position of the obtained absolute value is modified by using the normalizing shifter so as to give a mantissa part, and a value of an exponent part is generated by using the updater and the bit position decoder.

Abstract: In an absolute value subtraction processing of .vertline.X-Y.vertline., carry generation and propagation functions and group carry generation and propagation functions are first generated. Then, a carry is calculated at the most significant bit in the summation of a first operand and a complement of "2" of a second operand by use of the above functions. Where the carry is "1", the above summation remains continued. Where the carry is zero, additional first and second functions are generated by inverting logic ORs of the carry generation and propagation functions and of the group carry generation and propagation functions. Thus, the summation of the second operand and a complement of "2" of the first operand is realized by use of the additional functions, the carry propagation function, and the group carry propagation function.