Patents by Inventor Günter Gerstmeier
Günter Gerstmeier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7393721Abstract: A metallization surface (5), which acts as an etching stop layer during the production of openings (4) in a passivation layer (3) applied to its upper face and protects an interconnect structure (6) arranged underneath it, is arranged in an uppermost metallization level (1). A further opening is produced in the metal surface (5), through which a focused ion beam is aimed at the interconnect structure (6) in order to connect interconnects to one another and/or to interrupt at least one interconnect. The wiring of the integrated circuit can thus be varied individually, starting from identically produced semiconductor chips.Type: GrantFiled: May 12, 2005Date of Patent: July 1, 2008Assignee: Infineon Technologies AGInventors: Andreas Huber, Günter Gerstmeier, Michael Bernhard Sommer
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Patent number: 7304899Abstract: An integrated semiconductor memory includes programmable elements, which are arranged in a continuous region on a chip area of the integrated semiconductor memory. Operating parameters, for example, word line addresses of defective word lines are stored in the programmable elements in a compressed data format during the fabrication process of the integrated semiconductor memory. Upon activation of the integrated semiconductor memory, the compressed data are read out by a read-out circuit and fed to a decompression circuit. The decompression circuit generates, from a bit sequence of the compressed data with the aid of a decompression algorithm, a bit sequence of decompressed data which are evaluated by a control circuit. The storage of the operating parameters in the compressed data format and the arrangement of the programmable elements in a compact region significantly reduce the space requirement on the semiconductor chip.Type: GrantFiled: September 26, 2005Date of Patent: December 4, 2007Assignee: Infineon Technologies AGInventors: Günter Gerstmeier, Michael Bernhard Sommer
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Patent number: 7279881Abstract: An integrated circuit includes a voltage generator with a first controllable resistor and a second controllable resistor, through which a first input terminal that applies a first voltage potential and a second input terminal that applies a second voltage potential can be connected to an output terminal that generates an output voltage. In a manner dependent on the output voltage, a first comparator circuit generates a first control signal to control the first controllable resistor, and a second comparator circuit generates a second control signal to control the second controllable resistor. A control unit evaluates the control signals generated by the comparator circuits and drives the first and second controllable resistors of the voltage generator in such a way that in each case only one of the two controllable resistors has a low-resistance state.Type: GrantFiled: September 6, 2005Date of Patent: October 9, 2007Assignee: Infineon, AGInventors: Günter Gerstmeier, Michael Bernhard Sommer
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Patent number: 7163891Abstract: A dynamic random access memory (DRAM) structure having a distance less than 0.14 um between the contacts to silicon and the gate conductor is disclosed. In addition a method for forming the structure is disclosed, which includes forming the DRAM array contacts and the contacts to silicon simultaneously.Type: GrantFiled: December 3, 2004Date of Patent: January 16, 2007Assignee: Infineon Technologies AGInventors: Michael Maldei, Brian Cousineau, Guenter Gerstmeier, Jon S. Berry, II, Steven M. Baker, Jinhwan Lee
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Patent number: 7049193Abstract: A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes a plurality of transistors and the periphery region includes a plurality of transistors. The process includes depositing a middle-of-line liner using plasma enhanced chemical vapor deposition overlying the semiconductor structure. By using a plasma enhanced chemical vapor deposition the amount of MOL liner deposited in the core region and the periphery region can be controlled depending on the distances between transistors in the core region and periphery region.Type: GrantFiled: October 7, 2004Date of Patent: May 23, 2006Assignee: Infineon Technologies AGInventors: Michael Maldei, Jinhwan Lee, Guenter Gerstmeier, Brian Cousineau, Jon S. Berry, II, Steven M. Baker, Malati Hedge
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Patent number: 7035753Abstract: An integrated circuit having a signal bus carrying address signals includes mode selection means. The mode selection means has a default state and a non-default state. The integrated circuit is placed into a default and generic mode of operation when the mode selection means is in the default state. An address signal applied to the integrated circuit is interpreted as a specific mode of operation when the integrated circuit is in the default and generic mode of operation. The mode selection means when in the non-default state precludes placement of the integrated circuit into the default and generic mode of operation.Type: GrantFiled: March 20, 2002Date of Patent: April 25, 2006Assignee: Infineon Technologies AGInventors: Guenter Gerstmeier, Georg Antonischki, Shane Sanders, Marco Ziegelmaier
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Patent number: 6946889Abstract: A self-alignment system for complement clock signals includes a first delay circuit and a second delay circuit. A first clock signal may be propagated through the first delay circuit and a second clock signal may be propagated through the second delay circuit. A propagation delay of each of the first and second delay circuits may be selectively varied as a function of the first and second clock signals.Type: GrantFiled: February 11, 2003Date of Patent: September 20, 2005Assignee: Infineon Technologies AGInventors: Thoai-Thai Le, George Alexander, Guenter Gerstmeier
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Patent number: 6909152Abstract: A dynamic random access memory (DRAM) structure having a distance less than 0.14 ?m between the contacts to silicon and the gate conductor is disclosed. In addition a method for forming the structure is disclosed, which includes forming the DRAM array contacts and the contacts to silicon simultaneously.Type: GrantFiled: November 14, 2002Date of Patent: June 21, 2005Assignee: Infineon Technologies, AGInventors: Michael Maldei, Brian Cousineau, Guenter Gerstmeier, Jon S. Berry, II, Steven M. Baker, Jinhwan Lee
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Publication number: 20050130352Abstract: A dynamic random access memory (DRAM) structure having a distance less than 0.14 um between the contacts to silicon and the gate conductor is disclosed. In addition a method for forming the structure is disclosed, which includes forming the DRAM array contacts and the contacts to silicon simultaneously.Type: ApplicationFiled: December 3, 2004Publication date: June 16, 2005Inventors: Michael Maldei, Brian Cousineau, Guenter Gerstmeier, Jon Berry, Steven Baker, Jinhwan Lee
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Patent number: 6906371Abstract: A DRAM memory unit contains a memory bit (mbit) transistor and a capacitive region for storing charge. The memory is configured to store data as a charge stored by the capacitive region. Each memory unit is accessed by an associated wordline and the data stored by the memory unit is read from an associated bitline connected to the memory unit. The memory units are connected to the associated wordline via a wordline contact and connected to the associated bitline via a bitline contact. The memory units are arranged in memory unit clusters that include multiple memory units having a common bitline contact. The wordline contact is configured to provide for orientation of the wordlines in the memory array independent of the orientation of the bitlines. The wordline contact is also configured to provide for at least one wordline layer separated from the memory unit by a height of the wordline contact.Type: GrantFiled: August 12, 2002Date of Patent: June 14, 2005Assignee: Infineon Technologies AGInventors: Daivid SuitWai Ma, Guenter Gerstmeier
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Patent number: 6891404Abstract: A method of adjusting a control signal that includes generating a control signal at an unknown frequency and automatically adjusting the unknown frequency of the control signal based on the unknown frequency.Type: GrantFiled: June 11, 2002Date of Patent: May 10, 2005Assignee: Infineon TechnologiesInventors: Thoai-Thai Le, Juergen Lindolf, Guenter Gerstmeier
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Publication number: 20050062111Abstract: A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes a plurality of transistors and the periphery region includes a plurality of transistors. The process includes depositing a middle-of-line liner using plasma enhanced chemical vapor deposition overlying the semiconductor structure. By using a plasma enhanced chemical vapor deposition the amount of MOL liner deposited in the core region and the periphery region can be controlled depending on the distances between transistors in the core region and periphery region.Type: ApplicationFiled: October 7, 2004Publication date: March 24, 2005Inventors: Michael Maldei, Jinhwan Lee, Guenter Gerstmeier, Brian Cousineau, Jon Berry, Steven Baker, Malati Hedge
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Patent number: 6847092Abstract: A capacitor for a semiconductor device and a method of manufacturing a capacitor for a semiconductor device is disclosed that uses radial current flow. The capacitor includes a semiconductor substrate that includes a plurality of insulation islands. An insulation layer is formed over the semiconductor substrate. Gate electrodes are formed on top of the insulation layer. An array of CD contact pads including a plurality of CD contacts are connected to the semiconductor substrate in a first predetermined number of locations. An array of CG contact pads including at least one CG contact connected to the gate electrodes such that each CG contact is connected to a respective gate electrode above a respective insulation island in a second predetermined number of locations.Type: GrantFiled: March 6, 2003Date of Patent: January 25, 2005Assignee: Infineon Technologies AGInventors: Michael Maldei, Malati Hegde, Guenter Gerstmeier, Jinwhan Lee, Steven M. Baker, Jon S. Berry, II, Brian Cousineau, Wenchao Zheng
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Patent number: 6822301Abstract: A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes a plurality of transistors and the periphery region includes a plurality of transistors. The process includes depositing a middle-of-line liner using plasma enhanced chemical vapor deposition overlying the semiconductor structure. By using a plasma enhanced chemical vapor deposition the amount of MOL liner deposited in the core region and the periphery region can be controlled depending on the distances between transistors in the core region and periphery region.Type: GrantFiled: July 31, 2002Date of Patent: November 23, 2004Assignee: Infineon Technologies AGInventors: Michael Maldei, Jinhwan Lee, Guenter Gerstmeier, Brian Cousineau, Jon S. Berry, II, Steven M. Baker, Malati Hedge
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Publication number: 20040173868Abstract: A capacitor for a semiconductor device and a method of manufacturing a capacitor for a semiconductor device is disclosed that uses radial current flow. The capacitor includes a semiconductor substrate that includes a plurality of insulation islands. An insulation layer is formed over the semiconductor substrate. Gate electrodes are formed on top of the insulation layer. An array of CD contact pads including a plurality of CD contacts are connected to the semiconductor substrate in a first predetermined number of locations. An array of CG contact pads including at least one CG contact connected to the gate electrodes such that each CG contact is connected to a respective gate electrode above a respective insulation island in a second predetermined number of locations.Type: ApplicationFiled: March 6, 2003Publication date: September 9, 2004Inventors: Michael Maldei, Malati Hegde, Guenter Gerstmeier, Jinwhan Lee, Steven M. Baker, Jon S. Berry, Brian Cousineau, Wenchao Zheng
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Publication number: 20040160253Abstract: A self-alignment system for complement clock signals includes a first delay circuit and a second delay circuit. A first clock signal may be propagated through the first delay circuit and a second clock signal may be propagated through the second delay circuit. A propagation delay of each of the first and second delay circuits may be selectively varied as a function of the first and second clock signals.Type: ApplicationFiled: February 11, 2003Publication date: August 19, 2004Inventors: Thoai-Thai Le, George Alexander, Guenter Gerstmeier
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Publication number: 20040094810Abstract: A dynamic random access memory (DRAM) structure having a distance less than 0.14 um between the contacts to silicon and the gate conductor is disclosed. In addition a method for forming the structure is disclosed, which includes forming the DRAM array contacts and the contacts to silicon simultaneously.Type: ApplicationFiled: November 14, 2002Publication date: May 20, 2004Applicant: Infineon Technologies North America Corp.Inventors: Michael Maldei, Brian Cousineau, Guenter Gerstmeier, Jon S. Berry, Steven M. Baker, Jinhwan Lee
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Patent number: 6721180Abstract: A cooling hood for a circuit board is provided. The circuit board includes at least one semiconductor device. The cooling hood includes a duct mounted onto the circuit board and surrounding at least a portion of the semiconductor device. The duct forms an inlet and an outlet. A cooling medium enters the duct through the inlet and exits the duct through the outlet.Type: GrantFiled: July 31, 2002Date of Patent: April 13, 2004Assignee: Infineon Technologies AGInventors: Thoai-Thai Le, Guenter Gerstmeier, David SuitWai Ma, Tao Wang
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Publication number: 20040051166Abstract: A shielding line system reduces or eliminates crosstalk between conductive lines in an integrated circuit. The shielding line system has first conductive line and one or more second conductive lines. A shielding line conduit radially encloses the first conductive line. An electromagnetic field also radially encloses the first conductive line.Type: ApplicationFiled: September 18, 2002Publication date: March 18, 2004Inventors: Guenter Gerstmeier, Torsten Partsch
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Publication number: 20040026763Abstract: A DRAM memory unit contains a memory bit (mbit) transistor and a capacitive region for storing charge. The memory is configured to store data as a charge stored by the capacitive region. Each memory unit is accessed by an associated wordline and the data stored by the memory unit is read from an associated bitline connected to the memory unit. The memory units are connected to the associated wordline via a wordline contact and connected to the associated bitline via a bitline contact. The memory units are arranged in memory unit clusters that include multiple memory units having a common bitline contact. The wordline contact is configured to provide for orientation of the wordlines in the memory array independent of the orientation of the bitlines. The wordline contact is also configured to provide for at least one wordline layer separated from the memory unit by a height of the wordline contact.Type: ApplicationFiled: August 12, 2002Publication date: February 12, 2004Inventors: David SuitWai Ma, Guenter Gerstmeier