Abstract: A cooling hood for a circuit board is provided. The circuit board includes at least one semiconductor device. The cooling hood includes a duct mounted onto the circuit board and surrounding at least a portion of the semiconductor device. The duct forms an inlet and an outlet. A cooling medium enters the duct through the inlet and exits the duct through the outlet.

Abstract: A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes a plurality of transistors and the periphery region includes a plurality of transistors. The process includes depositing a middle-of-line liner using plasma enhanced chemical vapor deposition overlying the semiconductor structure. By using a plasma enhanced chemical vapor deposition the amount of MOL liner deposited in the core region and the periphery region can be controlled depending on the distances between transistors in the core region and periphery region.

Abstract: A method of adjusting a control signal that includes generating a control signal at an unknown frequency and automatically adjusting the unknown frequency of the control signal based on the unknown frequency.

Abstract: An integrated circuit having a signal bus carrying address signals includes mode selection means. The mode selection means has a default state and a non-default state. The integrated circuit is placed into a default and generic mode of operation when the mode selection means is in the default state. An address signal applied to the integrated circuit is interpreted as a specific mode of operation when the integrated circuit is in the default and generic mode of operation. The mode selection means when in the non-default state precludes placement of the integrated circuit into the default and generic mode of operation.

Abstract: Circuit configurations for testing transistors are arranged in the scribe line between integrated circuits on a semiconductor wafer. In order to increase the number of testable transistors while consuming little surface area, the transistors are arranged in a matrix in at least two rows. The drain-source paths of the transistors in the first row are connected between pads, and their gate connections are connected to a common pad. The drain-source paths of the transistors in the second row are connected firstly to one of the pads, and are secondly jointly connected to a further pad. Their gate connections are likewise connected to a further pad. The matrix-like arrangement of the transistors can be extended by using additional rows.

Abstract: In a method for examining structures on a wafer, at least one mask, which is applied on the wafer and is fabricated by exposure processes, is used for fabricating the structures. Test circuits with test structures are placed on the mask in predetermined reference positions. In order to check the structures and/or the exposure processes, electrical parameters of the test circuits are detected and evaluated in a location-dependent manner.