Abstract: A chip arrangement (1) has a substrate board (2) with an opening (3), into which a carrier chip (4) is inserted, which has an electrical or electronic structural component (5). At least one conductor path (7) is integrated into the carrier chip (4), which connects the structural component (5) to the electrical connection contact (8). The carrier chip (4) is inserted into the opening (3) in such a way that its ends project beyond the opposite-facing, flat-sided surfaces (9, 9′) of the substrate board (2), and thereby form overhangs (10, 10′). Here, the structural component is arranged on the overhang (10) projecting beyond the one surface (9), and the connection contact (8) is arranged on the overhang (10′) projecting beyond the other surface (9′), and the conductor path (7) connecting the structural component (5) and the connection contact (8) passes through the opening (3). A seal is arranged between the substrate board (2) and the carrier chip (4).

Abstract: A semiconductor component (1a) has a highly-doped substrate (4) of a first type of doping into which a highly-doped layer (15) of a second type of doping is introduced in some areas to form a pn Zener junction (16), and a low-doped area (17) of the second type of doping extends from this highly-doped layer (15) in the substrate (4) into an epitaxial layer (5) as far as the substrate (4) of the epitaxial layer (5). A Schottky metal (11) at least partially covering the low-doped, diffused area (17) is applied to the side of the epitaxial layer (5) facing away from the substrate (4) to form a Schottky junction (18) between this area (17) and the Schottky metal (11) and another Schottky junction (13) between the Schottky metal and the epitaxial layer (5). Due to the series connection of the oppositely polarized Zener diode and Schottky diode, a low temperature coefficient is achieved.

Abstract: The invention relates to an overvoltage protection device and to a method for fabricating such a device. A substrate (1) is provided with a first electrode layer (2), above which extends a second electrode layer (3) which is separated from the first electrode layer (2) by a distance (d) determined by the thickness of a spacing layer (4). The spacing layer (4) has an opening (5) which forms a cavity (6) between the electrode layers (2, 3).

Abstract: A process is provided for manufacturing a layer arrangement (1) having a bump for a flip chip or similar connection. The layer arrangement has a plurality of layers (2, 3, 4, 5, 6, 7, 11) made of solid material and stacked into a layer stack (8). A recess (10) that extends over several layers (2, 3, 4, 5, 6, 7, 11) is made in the layer stack (8) transverse to the coating planes of the layers (2, 3, 4, 5, 6, 7, 11). A bump material (14) is placed in the recess (10). A profiling is created on the lateral boundary wall of the recess (10) by removal of layer material of different layers (2, 3, 4, 5, 6, 7, 11) of the layer stack (8). The profiling, starting from the surface (9) of the layer stack (8) and progressing in layers to the inside of the recess (10), has at least two indentations (12) and at least one projection (13) located between them. After the production of the profiling, a bump material (14) is brought into the recess (10) in such a way that it grasps behind the indentations (12).

Abstract: A process is disclosed for fabricating a semiconductor device with a patterned metal layer (9). A layer (7) of a material with poor adhesion capability to the metal is deposited on the surface of a semiconductor substrate. On the layer (7), pattern lines (8) separated by a distance a are formed of a material with good adhesion capability to the metal, and the metal layer (9) is deposited such that by suitable choice of the ratio of the distance a to its thickness d and of its material properties, the metal layer (9) is caused to adhere only to the pattern lines (8) and to the area of the layer (7) between the pattern lines (8).

Abstract: There is disclosed a process for producing electronic devices from a semiconductor wafer. The process comprises forming separation regions with a spatial pattern on the semiconductor wafer to provide separation between electronic devices, and depositing a conductive contact layer on the wafer and patterning the contact layer in such a way that conductive terminals extend from the front side of the wafer over at least part of the cross section of the patterned separation regions. The terminals are bared by removing material of the wafer in the semiconductor regions starting from the backside of the wafer, and the terminals of adjacent electronic devices are separated.

Abstract: A process is disclosed for fabricating a device with a cavity formed at one end thereof. A body is provided with a depression, and mask layer is applied to the surface of the body and the depression, the mask layer having a lower etch rate than the body. Near the depression, an opening is formed in the mask layer. Starting from the opening, the body is subjected to an isotropic etching process to form the cavity below the mask layer, with the mask layer being essentially preserved and forming in the area of the depression a structure extending into the cavity.

Abstract: The invention relates to a process for manufacturing a sensor with a metal electrode in an MOS structure. During the MOS process, a sensing region with a structure for the metal electrode is formed, this structure being made of a material having predetermined adhesion properties for metals, the sensing region being uncovered by etching the passivating layer, and a metallization of the surface of the MOS structure being carried out in which the metal layer adheres only to the structure for the metal electrode.

Abstract: A process is disclosed for producing spatially patterned components from a body. On the backside of the body, a retardation layer with openings is provided for retarding a removal of the material of the body, and areas of migration-capable material are deposited. The body is subjected to a thermal migration process to form migration regions. Then, in a single material removal step, the components are separated from the body and the migration regions are exposed.

Abstract: A process for separating electronic devices connected with one another in a body, the process including thinning the side of the body remote from the electronic devices, separating the electronic devices, and testing electrical parameters of the electronic devices after the thinning of the body. The handling of the body is improved by applying to the side of the body containing the electronic devices, prior to the thinning process, an electrically nonconductive auxiliary layer in which respective contact openings are formed above the electronic devices to expose the contact(s) of the respective electronic device.

Abstract: A semiconductor device having a semiconductor substrate and an epitaxial layer deposited thereon which supports a patterned insulating layer on which a metal layer is provided. To achieve a lower capacitance of the semiconductor device with unchanged forward voltage, the epitaxial layer consists of first and second epitaxial layers, the first epitaxial layer which adjoins the semiconductor substrate having a higher dopant concentration than and being of the same conductivity type as the second epitaxial layer.