Abstract: A method for removing structures from a substrate is described. The method includes providing a substrate that has the structures that must be removed, applying a sacrifice layer, and removing the structures and the sacrifice layer in a polishing step. The method has the advantage that the sacrifice layer surrounds the structures that must be removed and stabilizes them, so that the structures can be eroded slowly and successively in the subsequent polishing step without breaking off. This prevents a smearing of the material of the structures such as occurs given direct polishing without a sacrifice layer.

Abstract: A method for producing a ferroelectric layer includes preparing a substrate, applying a layer of material, which will be subsequently converted into the ferroelectric layer, and changing the material into the ferroelectric layer by applying an outer electrical field aligned with the direction desired in the ferroelectric material and heat treating the material. By providing a first noble metal electrode on the surface before applying the material that is to become the ferroelectric layer and then subsequently forming a second noble metal electrode on the ferroelectric layer, a ferroelectric storage capacitor can be formed. If the substrate is provided with memory cells, which include at least one transistor for each cell and the above-mentioned ferroelectric storage capacitors, a ferroelectric memory arrangement can be produced.

Abstract: An interconnect arrangement (100) has a first layer (101), a first layer surface (102), thereon at least two interconnects (104) having a second layer surface (105) essentially parallel to the first layer surface (102), thereon a respective second layer (106) for each interconnect (104), the second layers (106) of adjacent interconnects covering regions between the adjacent interconnects (104), and thereon a third layer (107), which completely closes off the regions between the adjacent interconnects (104) by means of coverage.

Abstract: A method for structuring ferroelectric layers on semiconductor substrates retains or regenerates the adherence and breakdown voltage resistance of the ferroelectric layer, which is especially significant for producing storage capacitors in large-scale integrated FeRAM and DRAM memory components. The addition of H2O or O2 results principally in the recovery of the electrostatic breakdown strength of the ferroelectric layer, which is of importance in particular when the ferroelectric serves as a dielectric of a storage capacitor and has to withstand electric fields of 5-10×106 V/m without a significant leakage current.

Abstract: A method is described for producing a conducting connection through insulating layers by way of a contact hole and conducting materials with which the contact hole is filled. The method permits the production of a contact hole resembling the shape of a wineglass, into which conducting filling material and barrier layers can be inserted without the known problems such as void formation, overetching trenches, and dielectric close-off. It is possible in this way, for example, to produce an electric connection between the diffusion zone of a selection transistor and the lower electrode of a storage capacitor of large-scale integrated DRAM and FeRAM components with the aid of only a few mask steps.

Abstract: The invention relates to a monitoring system for a conveying device for flat articles, especially wafers, which conveying device is provided with a carriage (28) that is movable along a predetermined path next to a flat article (10) that is located at a predetermined removal location, the carriage having a receiving device for the accommodation of the flat article (10), which monitoring system contains a light source (50) having a light-exit window and a light receiver (52) having a light-admission window, whereby the light-exit window and the light-admission window are positioned in such a way that a light beam (60) directed form the light-exit window to the light-admission window is partially covered by the carriage (28) during its movement through the light beam, and an evaluation unit that is connected to the light receiver and that compares a target signal derived from its movement of the carriage along a target path with an actual signal derived from an actual movement of the carriage, and indicates a d

Abstract: The invention provides a semiconductor memory component with random access, also having a structure which is differentiated into memory cells and logic regions and has a lower oxide layer arranged on a silicon substrate and an upper oxide layer arranged on the lower oxide layer, each memory cell comprising at least one transistor in the transition region between silicon substrate and lower oxide layer and a capacitor in the transition region between lower oxide layer and upper oxide layer, which capacitor is connected to the transistor via a contact hole, which is filled with metal, in the lower oxide layer and comprises a ferroelectric arranged between two electrodes, the electrode which is connected to the transistor and adjoins the lower oxide layer having a relatively great thickness, and each logic region comprising at least one transistor in the transition region between silicon substrate and lower oxide layer, which transistor is connected to an electrode on the topside of the upper oxide layer via a c

Abstract: A method for fabricating a semiconductor component includes the steps of applying an electrode material and a metal-oxide-containing layer on a substrate surface and selectively etching the electrode material and the metal-oxide-containing layer for forming a first electrode from the electrode material and forming a metal oxide layer from the metal-oxide-containing layer, wherein the metal oxide layer is disposed on top of the first electrode. The method further includes conformally applying a conductive material which has a given material thickness, anisotropically etching the conductive material for fabricating a resistance element in the form of a self-aligned lateral edge web on at least one sidewall of the metal oxide layer and of the first electrode, and applying a further electrode material at least on the resistance element for forming a second electrode.

Abstract: A method of fabricating semiconductor circuits having integrated capacitors that have a dielectric or a ferroelectric material between electrodes. The materials are subjected to heat treatment at high temperatures in an oxygen atmosphere for the purpose of crystallization. The dielectric or ferroelectric is heated separately from the semiconductor substrate, is comminuted into small particles and only afterward applied in this form to the semiconductor substrate. This makes it possible to integrate substances with arbitrarily high crystallization temperature without damaging the integrated semiconductor circuit, since the semiconductor substrate itself does not have to be heated. Diffusion barriers for oxygen are unnecessary. Previous limitations on the capacitor capacitance are obviated owing to the free choice of dielectric or ferroelectric made possible, and the packing density of the capacitors is increased.

Abstract: A method for fabricating a microelectronic component includes the step of applying a barrier against the passage of hydrogen to a storage capacitor having a ferroelectric dielectric or a paraelectric dielectric. During the formation of the barrier, firstly a silicon oxide layer is produced, the latter is then subjected to a heat treatment and a barrier layer is subsequently applied. A microelectronic component has a storage capacitor and a barrier including a silicon oxide layer and a barrier layer. The silicon oxide layer is disposed on an electrode of the storage capacitor and has been subjected to a heat treatment in an oxygen-containing atmosphere. The barrier layer is disposed on the silicon oxide layer and protects the storage capacitor against a passage of hydrogen through the barrier.

Abstract: A semiconductor memory configuration has a plurality of selection transistors. Each selection transistor is connected to a first electrode of a storage capacitor. A second electrode of the storage capacitor is connected to a common plate. The common plate is provided below the selection transistors in a semiconductor body. A method of fabricating a semiconductor memory configuration is also provided.

Abstract: A process for producing structured layers on a base body, in particular a semiconductor body, includes the steps of providing a first layer, structuring the first layer with a partial or complete local layer erosion to form raised and recessed layer regions, and depositing a second layer. The structured first layer is a provided as a permanently remaining layer. Edges are formed at transitions from raised to recessed layer regions. The height difference at the edges of the structured first layer separates individual layer regions of the second layer. The edges of the raised regions act as partition edges for the second layer. A process for producing components of an integrated circuit and a process for producing a memory configuration are also provided.

Abstract: The invention relates to a method for producing at least one capacitor structure, comprising the following steps: providing a substrate, producing a first electrode on said substrate, producing a mask, whereby the first electrode is disposed in an opening of said mask, and applying at least one dielectric layer and at least one conductive layer for a second eletrode. The surface of the part of the conductive layer that is applied in the opening of the mask is substantially disposed below the surface of the mask. The conductive layer and the dielectric layer are structured by polishing so that a capacitor structure is produced.

Abstract: A method for producing a ferroelectric layer includes preparing a substrate, applying a layer of material, which will be subsequently converted into the ferroelectric layer, and changing the material into the ferroelectric layer by applying an outer electrical field aligned with the direction desired in the ferroelectric material and heat treating the material. By providing a first noble metal electrode on the surface before applying the material that is to become the ferroelectric layer and then subsequently forming a second noble metal electrode on the ferroelectric layer, a ferroelectric storage capacitor can be formed. If the substrate is provided with memory cells, which include at least one transistor for each cell and the above-mentioned ferroelectric storage capacitors, a ferroelectric memory arrangement can be produced.

Abstract: After an SBT layer is precipitated onto a substrate, the SBT layer is structured as a still amorphous layer. Only subsequently is it subjected to a crystallization process. Layers produced in this manner have a relatively high degree of dielectric strength and have no stoichiometric deviations on the etched edges.

Abstract: A method of producing a ferroelectric semiconductor memory, includes forming a switching transistor on a semiconductor substrate, applying an insulating layer to the switching transistor and then forming a storage capacitor, with electrodes of platinum and a ferroelectric or paraelectric dielectric, on the insulating layer. In order to protect the dielectric from being penetrated by hydrogen during further process steps, a first barrier layer is embedded into the insulating layer and, after completion of the storage capacitor, a second barrier layer, which bonds with the first barrier layer, is deposited.

Abstract: In a method for fabricating a high-epsilon dielectric/ferroelectric capacitor, a patterning layer with a central base layer zone and a Si-filled trench laterally surrounding the latter is produced. Above that, a metal layer is deposited and is silicided above the Si-filled trench. Through oxidation of the silicided metal layer section the latter migrates into the trench and a base electrode is formed above the base layer zone.

Abstract: A random access memory having a multiplicity of memory cells having logic states that can be changed by a control voltage. At least some of the memory cells include an additional device that can be activated by means of an enforced control voltage that is different from the control voltage, in order to impress a defined logic state on the memory cell.

Abstract: The damage to edge sections which occurs during the patterning of a metal-oxide-containing layer can be compensated by the deposition of an annealing layer and a subsequent heat treatment step through which a material flow takes place from the annealing layer into the damaged edge sections. The metal-oxide-containing layer can form the dielectric of a storage capacitor of a DRAM memory cell.

Abstract: The invention provides a method. In a first step of a method for fabricating a ferroelectric memory configuration, there is provided a substrate having a multiplicity of memory cells. Each of the memory cells has at least one select transistor, at least one short-circuit transistor, and at least one ferroelectric capacitor. The transistors are connected in an electrically conductive manner to a first of the electrodes of the ferroelectric capacitor. In the next step, at least one electrically insulating layer is applied. In the next step, at least one contact hole for connecting a second electrode of the ferroelectric capacitors is produced. Next, contact holes for connecting the short-circuit transistors are produced. Next, the contact holes are filled with electrically conductive material. Next, an electrically conductive layer is applied and patterned, so that the second electrodes of the ferroelectric capacitors are each conductively connected to the short-circuit transistors.