Abstract: The invention relates to a semiconductor component comprising a semiconductor body, an insulation on the semiconductor body and a cell array arranged at least partly within the semiconductor body. The cell array has at least one p-n junction and at least one contact connection. The insulation is bounded in lateral direction of the semiconductor body by a circumferential diffusion barrier.

Abstract: An interconnect arrangement and fabrication method are described. The interconnect arrangement includes an electrically conductive mount substrate, a dielectric layer formed on the mount substrate, and an electrically conductive interconnect formed on the dielectric layer. At least a portion of the dielectric layer under the interconnect contains a cavity. To fabricate the interconnect arrangement, a sacrificial layer is formed on the mount substrate and the interconnect layer is formed on the sacrificial layer. The interconnect layer and the sacrificial layer are structured to produce a structured interconnect on the structured sacrificial layer. A porous dielectric layer is formed on a surface of the mount substrate and of the structured interconnect as well as the sacrificial layer. The sacrificial layer is then removed to form the cavity under the interconnect.

Abstract: An MIM capacitor includes a first capacitor electrode, which is formed in the surface of a first intermediate dielectric, a second intermediate dielectric, which is formed on the first intermediate dielectric and has an opening that exposes the first capacitor electrode, and a first electrically conducting diffusion barrier layer, which is formed on the surface of the exposed first capacitor electrode. On the diffusion barrier layer and on the side walls of the opening there is also formed a capacitor dielectric and a second capacitor electrode on top.

Abstract: The invention relates to a semiconductor component comprising a semiconductor body, an insulation on the semiconductor body and a cell array arranged at least partly within the semiconductor body. The cell array has at least one p-n junction and at least one contact connection. The insulation is bounded in lateral direction of the semiconductor body by a circumferential diffusion barrier.

Abstract: An MIM capacitor includes a first capacitor electrode, which is formed in the surface of a first intermediate dielectric, a second intermediate dielectric, which is formed on the first intermediate dielectric and has an opening that exposes the first capacitor electrode, and a first electrically conducting diffusion barrier layer, which is formed on the surface of the exposed first capacitor electrode. On the diffusion barrier layer and on the side walls of the opening there is also formed a capacitor dielectric and a second capacitor electrode on top.

Abstract: An MIM capacitor includes a first capacitor electrode, which is formed in the surface of a first intermediate dielectric, a second intermediate dielectric, which is formed on the first intermediate dielectric and has an opening that exposes the first capacitor electrode, and a first electrically conducting diffusion barrier layer, which is formed on the surface of the exposed first capacitor electrode. On the diffusion barrier layer and on the side walls of the opening there is also formed a capacitor dielectric and a second capacitor electrode on top.

Abstract: An interconnect arrangement and fabrication method are described. The interconnect arrangement includes an electrically conductive mount substrate, a dielectric layer formed on the mount substrate, and an electrically conductive interconnect formed on the dielectric layer. At least a portion of the dielectric layer under the interconnect contains a cavity. To fabricate the interconnect arrangement, a sacrificial layer is formed on the mount substrate and the interconnect layer is formed on the sacrificial layer. The interconnect layer and the sacrificial layer are structured to produce a structured interconnect on the structured sacrificial layer. A porous dielectric layer is formed on a surface of the mount substrate and of the structured interconnect as well as the sacrificial layer. The sacrificial layer is then removed to form the cavity under the interconnect.

Abstract: In a method for manufacturing a layer arrangement, a plurality of electrically conductive structures are embedded in a substrate. Material of the substrate is removed at least between adjacent electrically conductive structures. An interlayer is formed on at least one portion of sidewalls of each of the electrically conductive structures. A first layer is formed on the interlayer where an upper partial region of the interlayer remaining free of a covering with the first layer. An electrically insulating second layer is formed selectively on that partial region of the interlayer which is free of the first layer, in such a way that the electrically insulating second layer bridges adjacent electrically conductive structures such that air gaps are formed between adjacent electrically conductive structures.

Abstract: A method for producing a layer arrangement is disclosed. A layer of oxygen material and nitrogen material is formed over a substrate that has a plurality of electrically conductive structures and/or over a part of a surface of the electrically conductive structures. The layer is formed using a plasma-enhanced chemical vapor deposition process with nitrogen material being supplied during the supply of silicon material and oxygen material by means of an organic silicon precursor material. The layer of oxygen material and nitrogen material is formed in such a manner that an area free of material remains between the electrically conductive structures. An intermediate layer including an electrically insulating material is formed over the layer of oxygen material and nitrogen material. A covering layer is selectively formed over the intermediate layer such that the area free of material between the electrically conductive structures is sealed from the environment and forms a cavity.

Abstract: A method for producing a layer arrangement is disclosed. A layer of oxygen material and nitrogen material is formed over a substrate that has a plurality of electrically conductive structures and/or over a part of a surface of the electrically conductive structures. The layer is formed using a plasma-enhanced chemical vapor deposition process with nitrogen material being supplied during the supply of silicon material and oxygen material by means of an organic silicon precursor material. The layer of oxygen material and nitrogen material is formed in such a manner that an area free of material remains between the electrically conductive structures. An intermediate layer including an electrically insulating material is formed over the layer of oxygen material and nitrogen material. A covering layer is selectively formed over the intermediate layer such that the area free of material between the electrically conductive structures is sealed from the environment and forms a cavity.

Abstract: In a method for manufacturing a layer arrangement, a plurality of electrically conductive structures are embedded in a substrate. Material of the substrate is removed at least between adjacent electrically conductive structures. An interlayer is formed on at least one portion of sidewalls of each of the electrically conductive structures. A first layer is formed on the interlayer where an upper partial region of the interlayer remaining free of a covering with the first layer. An electrically insulating second layer is formed selectively on that partial region of the interlayer which is free of the first layer, in such a way that the electrically insulating second layer bridges adjacent electrically conductive structures such that air gaps are formed between adjacent electrically conductive structures.

Abstract: The invention relates to a microelectronic structure which provides improved protection of a hydrogen-sensitive dielectric against hydrogen contamination. According to the invention, the hydrogen sensitive dielectric (14) is covered at lest by an intermediate oxide (18), where material thickness is at lest five times the thickness of the hydrogen-sensitive dielectric. The intermediate oxide (18) simultaneously acts as an internal dielectric and is metabolized on its surface for this purpose. The intermediate oxide (18), which has a sufficient thickness absorbers the hydrogen that may be released during the deposition of a hydrogen barrier layer (22, 26), thus protecting the hydrogen-sensitive dielectric (14).

Abstract: An integrated circuit having a multilayer capacitance arrangement and a method for producing an integrated circuit having a multilayer capacitance arrangement are disclosed.

Abstract: To store information in a ferroelectric material, a sample probe is used to bring about mechanical action on individual domains and thereby to cause a reversal of polarization in the individual domains, with electrodes situated below the ferroelectric material being able to have a bias applied to them to stabilize the change/reversal of polarization. The reversal of polarization causes an alteration in the surface topography of the ferroelectric material, and this alteration can be used to read the information. The stored information is therefore obtained by ascertaining the surface topography of the ferroelectric material. The information is written and read using an AFM tip, with the tip being able to be operated in contact or tapping mode for the purpose of writing, and additionally in noncontact mode for the purpose of reading.

Abstract: A conductor track arrangement includes a substrate, at least two conductor tracks, a cavity and a resist layer that covers the conductor tracks and closes off the cavity. By forming carrier tracks with a width less than a width of the conductor tracks, air gaps can also be formed laterally underneath the conductor tracks for reducing the coupling capacitances and the signal delays in a self-aligning manner.

Abstract: An MIM capacitor includes a first capacitor electrode, which is formed in the surface of a first intermediate dielectric, a second intermediate dielectric, which is formed on the first intermediate dielectric and has an opening that exposes the first capacitor electrode, and a first electrically conducting diffusion barrier layer, which is formed on the surface of the exposed first capacitor electrode. On the diffusion barrier layer and on the side walls of the opening there is also formed a capacitor dielectric and a second capacitor electrode on top.

Abstract: An interconnect arrangement and fabrication method are described. The interconnect arrangement includes an electrically conductive mount substrate, a dielectric layer formed on the mount substrate, and an electrically conductive interconnect formed on the dielectric layer. At least a portion of the dielectric layer under the interconnect contains a cavity. To fabricate the interconnect arrangement, a sacrificial layer is formed on the mount substrate and the interconnect layer is formed on the sacrificial layer. The interconnect layer and the sacrificial layer are structured to produce a structured interconnect on the structured sacrificial layer. A porous dielectric layer is formed on a surface of the mount substrate and of the structured interconnect as well as the sacrificial layer. The sacrificial layer is then removed to form the cavity under the interconnect.

Abstract: An interconnect arrangement comprises a substrate made from a first insulating material with a substrate surface, at least two interconnects which are arranged next to one another in the substrate, a buffer layer made from a second insulating material above the substrate and comprising a buffer-layer surface, which is parallel to the substrate surface, at least one cavity, which is arranged between the interconnects and, with respect to the buffer-layer surface, extends deeper into the substrate than the interconnects, and a covering layer made from a third insulating material, which is arranged above the buffer layer and completely closes off the cavity with respect to the buffer-layer surface.

Abstract: An interconnect arrangement (100) has a first layer (101), a first layer surface (102), thereon at least two interconnects (104) having a second layer surface (105) essentially parallel to the first layer surface (102), thereon a respective second layer (106) for each interconnect (104), the second layers (106) of adjacent interconnects covering regions between the adjacent interconnects (104), and thereon a third layer (107), which completely closes off the regions between the adjacent interconnects (104) by means of coverage.

Abstract: A ferroelectric capacitor configuration is configured with at least two different coercitive voltages. A first electrode structure having a surface which forms at least two levels is firstly produced. A layer of ferroelectric material of varying thickness is deposited over the first electrode by spin coating. A second electrode structure is subsequently formed on the layer of ferroelectric material.