Patents by Inventor Gajender Rohilla

Gajender Rohilla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7598812
    Abstract: A method and an apparatus are described for shorted input detection for amplifier circuits. An embodiment of a circuit includes multiple amplifier circuits, with each amplifier circuit having an input and an output. The circuit also includes multiple short detection circuits, with one of the short detection circuits being coupled to the input of each amplifier circuit. Each short detection circuit has an active state for detection of short circuits and an inactive state for normal amplifier operation. The circuit also includes a register coupled with the output of each of the amplifier circuits to hold the output of one or more of the amplifier circuits.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: October 6, 2009
    Assignee: Cypress Semiconductor Corporation
    Inventors: Pulkit Shah, Gajender Rohilla
  • Publication number: 20080297388
    Abstract: A system includes an analog-to-digital modulator to convert at least one analog input signal into at least one digital output signal. The system also includes a processing device to set an operational order and a quantization level of the analog-to-digital modulator. The analog-to-digital modulator converts the analog input signal into the digital output signal according to the operational order and the quantization level.
    Type: Application
    Filed: March 31, 2008
    Publication date: December 4, 2008
    Applicant: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Eashwar Thiagarajan, Mohandas Palatholmana Sivadasan, Gajender Rohilla, Harold Kutz, Monte Mar
  • Patent number: 7424650
    Abstract: A method and test circuits for measuring skew between two circuit blocks of an integrated circuit. A first data signal is propagated through a first circuit block and a first clock signal is propagated through a second circuit block. The first data signal is latched synchronized to the first clock signal after propagating the first data and clock signals. The first data signal is time shifted relative to the first clock signal until the first data signal is no longer validly latching. A second data signal is propagated through the second circuit block and a second clock signal is propagated through the first circuit block. An inversion of the second data signal synchronized to an inversion of the second clock signal is latched. Then, the second data signal is time shifted relative to the second clock signal until the inversion of the second data signal is no longer validly latching.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: September 9, 2008
    Assignee: Cypress Semiconductor Corporation
    Inventors: Mohandas Palathol Mana Sivadasan, Gajender Rohilla
  • Publication number: 20080088368
    Abstract: A method and an apparatus are described for an offset correction in a high gain amplifier. An embodiment of an amplifier circuit includes an amplifier to convert a current signal into a voltage signal, where the amplifier generates an offset voltage in the voltage signal. The amplifier circuit also includes a sampling component coupled with the amplifier, with the sampling component subtracting a first sample of the voltage signal from a second sample of the voltage signal to produce a difference value. The amplifier circuit further includes a gain component coupled with the sampling component to amplify the difference between the first sample and the second sample.
    Type: Application
    Filed: December 6, 2006
    Publication date: April 17, 2008
    Inventor: Gajender Rohilla
  • Publication number: 20080001676
    Abstract: A method and an apparatus are described for shorted input detection for amplifier circuits. An embodiment of a circuit includes multiple amplifier circuits, with each amplifier circuit having an input and an output. The circuit also includes multiple short detection circuits, with one of the short detection circuits being coupled to the input of each amplifier circuit. Each short detection circuit has an active state for detection of short circuits and an inactive state for normal amplifier operation. The circuit also includes a register coupled with the output of each of the amplifier circuits to hold the output of one or more of the amplifier circuits.
    Type: Application
    Filed: June 12, 2007
    Publication date: January 3, 2008
    Inventors: Pulkit Shah, Gajender Rohilla
  • Patent number: 7280574
    Abstract: A circuit for driving a laser diode has a variable bias circuit. The variable bias circuit has an output designed to couple to the laser diode. A modulation circuit has an output designed to couple to the laser diode.
    Type: Grant
    Filed: May 15, 2002
    Date of Patent: October 9, 2007
    Assignee: Cypress Semiconductor Corp.
    Inventors: Vijay Khawshe, Gajender Rohilla
  • Publication number: 20070230525
    Abstract: One embodiment relates to an optical navigation apparatus which provides fault-tolerant limitation of laser output power. The apparatus includes a diode laser and a current source interconnected with the diode laser. Two independent circuits in the current source are configured to limit current flowing through the diode laser. Another embodiment relates to a method of providing fault-tolerant limitation of laser output power in an optical navigation apparatus. A first digital current limit value is converted to a first analog signal, and the first analog signal is used to limit an electrical current from a power supply connection to an anode of a diode laser. A second digital current limit value is converted to a second analog signal, and the second analog signal is used to limit an electrical current from a cathode of the diode laser to a ground connection. Other embodiments are also disclosed.
    Type: Application
    Filed: May 12, 2006
    Publication date: October 4, 2007
    Inventors: Steven Sanders, Gary Gibbs, Ashish Pancholy, Gajender Rohilla, Pulkit Shah
  • Patent number: 7190191
    Abstract: An input buffer circuit and associated method operable in a normal mode and a hot-plug mode. In one example, the input buffer has an input and a buffer output, and the input buffer may include a pull-up path coupled between a first circuit supply and the buffer output; a pull-down path coupled between the buffer output and a ground reference voltage; a first transistor coupled between the input and the pull-up path to activate the pull-up path; a second transistor coupled between the input and the pull-down path to activate the pull-down path; and a third transistor for protecting the pull-up path from over-voltage. The input buffer circuit may be configured to prevent an over-voltage condition on each of the plurality of transistors and the input buffer circuit may be configured to allow a hot-plug operation.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: March 13, 2007
    Assignee: Cypress Semiconductor Corporation
    Inventors: Manish Kumar Mathur, Gajender Rohilla
  • Patent number: 6980575
    Abstract: The present invention provides a circuit capable of driving a diode with multiple amounts of current with a low supply voltage without the requirement of alternating current coupling. The circuit provides for headroom voltage for the current sources allowing them to operate correctly without the requirement of external components such as inductors to provide coupling. The circuit may provide one of at least two different amounts of current depending upon the voltage of at least two inputs suitable for driving a vertical cavity surface emitting laser diode.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: December 27, 2005
    Assignee: Cypress Semiconductor Corp.
    Inventor: Gajender Rohilla
  • Patent number: 6933786
    Abstract: An amplifier system has a control circuit. An amplifier is coupled to the control circuit and has a controllable gain. A controllable input impedance circuit is coupled to the control circuit. When the gain of the amplifier is changed the controllable input impedance circuit's impedance is adjusted, so that the input impedance to the system remains essentially constant.
    Type: Grant
    Filed: May 15, 2002
    Date of Patent: August 23, 2005
    Assignee: Cypress Semiconductor Corporation
    Inventors: Palathol mana Sivadasan Mohandas, Gajender Rohilla, Pulkit Shah
  • Patent number: 6842320
    Abstract: Embodiments of the present invention provide a drive and biasing circuit for an input/output stage of a device. Embodiments of the present invention provide live-insertion protection by driving and biasing various nodes in the input/output stage. Embodiments of the present invention also provide over-voltage protection by biasing various nodes in the input/output stage during normal and live-insertion operating conditions. Embodiments of the present invention utilize the voltage on the supply and/or voltage present on the input/output terminal to provide the drive and bias voltage levels. Embodiments of the present invention are thus able to turn off current paths and protect various junctions against breakdown during over-voltage and live-insertion operating conditions.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: January 11, 2005
    Assignee: Cypress Semiconductor Corporation
    Inventors: Manish Kumar Mathur, Gajender Rohilla