Patents by Inventor Gajendra Singh

Gajendra Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9294211
    Abstract: Embodiments of the disclosure relate to a method and system for enhancing management channels. The method comprises operating TDM (Time Division Multiplex) clock frequency at a predefined rate higher than operating frequency based on available management channels. Transmitting data on the management channels using the TDM slots of a TDM based controller at a higher frequency rate.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: March 22, 2016
    Assignee: TEJAS NETWORKS LTD
    Inventors: Srinivas Rao, Gajendra Singh Ranka
  • Publication number: 20140187594
    Abstract: Described herein are compounds of formula (I), their derivatives, analogs, tautomeric forms, stereoisomers, polymorphs, hydrates, solvates, pharmaceutically acceptable salts and compositions, metabolites and prodrugs thereof, for use in treating liver diseases such as non-alcoholic fatty liver disease (NAFLD) and non-alcoholic steatohepatitis (NASH), and other fibrotic diseases of the liver; diabetic complications such as macro (ischemic heart disease, cerebrovascular disease and peripheral vascular disease) and micro (cataract, retinopathy nephropathy neuropathy, maculopathy and glaucoma) vascular complication; and cardiovascular diseases such as atherosclerosis, restenosis, hypertension, vasospasm, and cardiac hypertrophy; and lung disorders and lung fibrosis.
    Type: Application
    Filed: March 28, 2011
    Publication date: July 3, 2014
    Applicant: ORCHID CHEMICALS AND PHARMACEUTICALS LTD
    Inventors: Shridhar Narayanan, Jeyamurugan Mookkan, Jayanarayan Kulathingal, Narayanan Surendran, Gajendra Singh, Gopalan Balasubramanian
  • Publication number: 20140086261
    Abstract: The present disclosure discloses a system architecture and method for reducing pin count on a backplane connecting plurality of devices. In an embodiment, the signals from the plurality of devices are multiplexed or mapped into time slots using a MapMux device. The MapMux device then sends the multiplexed or mapped signals over backplane on TDM bus. The MapMux device at the receiving end de-multiplexes or de-maps and sends the received signals to plurality of devices for further processing. The present disclosure allows a large number of signals to be passed between the devices through a single stream.
    Type: Application
    Filed: July 8, 2011
    Publication date: March 27, 2014
    Applicant: TEJAS NETWORKS LIMITED
    Inventors: Srinivas Rao, Gajendra Singh Ranka
  • Publication number: 20140064302
    Abstract: Embodiments of the disclosure relate to a method and system for enhancing management channels. The method comprises operating TDM (Time Division Multiplex) clock frequency at a predefined rate higher than operating frequency based on available management channels. Transmitting data on the management channels using the TDM slots of a TDM based controller at a higher frequency rate.
    Type: Application
    Filed: July 7, 2011
    Publication date: March 6, 2014
    Applicant: TEJAS NETWORKS LIMITED
    Inventors: Srinivas Rao, Gajendra Singh Ranka
  • Publication number: 20140044119
    Abstract: Embodiments of the present disclosure relate to a method and system for multiplexing the low frequency signals from at least one clock transmitter to at least one clock receiver to reduce interface count. The low frequency signals are multiplexed in a CLKMUX logic using selection signals. The selection signals are generated using system frame and system clocks. The multiplexed clock is received by the CLKDEMUX logic through an interface. The interface can be backplane connectors, PCB traces and cables. The CLKDEMUX logic dc-multiplexes the received clock and transmits to the SELECT LOGIC for selecting at least one low frequency clock. The SELECT LOGIC selects at least one low frequency clock based on the signals from a processor. The jitter attenuator filters jitter in the low frequency clock and the CLOCK SINK distributes system clocks to rest of system elements.
    Type: Application
    Filed: July 8, 2011
    Publication date: February 13, 2014
    Applicant: TEJAS NETWORKS LIMITED
    Inventors: Srinivas Rao, Gajendra Singh Ranka
  • Publication number: 20140035635
    Abstract: The invention relates to an apparatus and a method for glitch-free clock switching. In one embodiment this is accomplished by a first clock source, one or more second clock source and a clock switching control device configured to synchronize the receive input clock from the first clock source and the second clock source, and output at least one of the them according to control signal selection.
    Type: Application
    Filed: August 11, 2011
    Publication date: February 6, 2014
    Applicant: Tejas Networks Limited Plot No. 25, JP Software Park
    Inventors: Srinivas Rao, Gajendra Singh Ranka
  • Publication number: 20140022887
    Abstract: Embodiments of the present disclosure relate to a Zero traffic hit synchronization switch over technique in a telecommunication network. The switch over is carried out by switching input reference of the receiver from one or more master (1) to at least one slave (2), wherein said slave (2) becomes new master (2) and said one or more master (1) becomes new slave (1) after switching. Now, the new master (2) locks to the new slave (1) for predetermined time period. Once the predetermined is elapsed, the new master (2) is disconnected from the new slave (1), wherein said new master (2) selects its own network reference clock upon disconnection of the new slave (1). The new slave (1) is locked to the new master (2) to synchronize the switchover in redundant systems.
    Type: Application
    Filed: July 7, 2011
    Publication date: January 23, 2014
    Applicant: TEJAS NETWORKS LIMITED
    Inventors: Srinivas Rao, Gajendra Singh Ranka
  • Patent number: 8466145
    Abstract: Described are novel compounds of the Formula (I), their derivatives, analogs, tautomeric forms, regioisomers, stereoisomers, polymorphs, solvates, intermediates, pharmaceutically acceptable salts, pharmaceutical compositions, metabolites and prodrugs thereof. These compounds are effective in lowering blood glucose, serum insulin, free fatty acids, cholesterol, triglyceride levels; treatment of obesity, inflammation, autoimmune diseases such as multiple sclerosis, rheumatoid arthritis; treatment and/or prophylaxis of type II diabetes. These compounds are more particularly dipeptidyl peptidase (DPP IV) inhibitors.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: June 18, 2013
    Assignee: Orchid Chemicals & Pharmaceuticals Limited
    Inventors: Gopalan Balasubramanian, Sukumar Sakamuri, Gajendra Singh, Sivanesan Dharmalingam, Franklin Pooppady Xavier, Shridhar Narayanan, Jeyamurugan Mookkan, Jeganatha Sivakumar Balasubramanian, Agneeswari Rajalingam, Jayanarayan Kulathingal
  • Patent number: D666967
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: September 11, 2012
    Assignee: Omni United (S) Pte Ltd.
    Inventor: Gajendra Singh Sareen
  • Patent number: D667366
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: September 18, 2012
    Assignee: Omni United (S) Pte Ltd.
    Inventor: Gajendra Singh Sareen
  • Patent number: D669019
    Type: Grant
    Filed: April 29, 2010
    Date of Patent: October 16, 2012
    Assignee: Omni United (S) Pte Ltd
    Inventor: Gajendra Singh Sareen
  • Patent number: D682188
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: May 14, 2013
    Assignee: Omni United (S) Pte Ltd.
    Inventor: Gajendra Singh Sareen
  • Patent number: D684923
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: June 25, 2013
    Assignee: Omni United (S) Pte Ltd
    Inventor: Gajendra Singh Sareen
  • Patent number: D700883
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: March 11, 2014
    Assignee: Omni United (S) Pte Ltd
    Inventor: Gajendra Singh Sareen
  • Patent number: D733039
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: June 30, 2015
    Assignee: OMNI UNITED (S) PTE LTD.
    Inventor: Gajendra Singh Sareen
  • Patent number: D733041
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: June 30, 2015
    Assignee: OMNI UNITED (S) PTE LTD.
    Inventor: Gajendra Singh Sareen
  • Patent number: D735121
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: July 28, 2015
    Assignee: OMNI UNITED (S) PTE LTD.
    Inventor: Gajendra Singh Sareen
  • Patent number: D743328
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 17, 2015
    Assignee: Omni United (S) Pte Ltd
    Inventor: Gajendra Singh Sareen
  • Patent number: D752504
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: March 29, 2016
    Assignee: Omni United (S) Pte Ltd.
    Inventor: Gajendra Singh Sareen
  • Patent number: D755117
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: May 3, 2016
    Assignee: Omni United (S) Pte Ltd
    Inventor: Gajendra Singh Sareen