Patents by Inventor Gajendra Singh

Gajendra Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070091104
    Abstract: This document discusses, among other things, a system and method for connecting a plurality of memory controllers to one or more memory modules. Each memory module includes an advanced memory buffer (AMB) connected to a plurality of memory devices. A switch is connected between the plurality of memory controllers and the one or more memory modules. A memory read request is routed from one of the plurality of memory controllers through the switch to a preselected memory module.
    Type: Application
    Filed: July 10, 2006
    Publication date: April 26, 2007
    Inventors: Gajendra Singh, Tzungren Tzeng, Rabin Sugumar
  • Publication number: 20070078472
    Abstract: Gajendra safe surgical knife has a hexagonal shape, capacity of retraction and protraction of blade and able to lock temporarily and permanently. This surgical knife can be protracted with a push of the base of inner sheath and can be retracted by gently pressing the holding button. The holding button is a spring loaded small mechanism which holds automatically the inner sheath and blade within it with the forward movement of inner sheath. A pressure on the holding button releases the knife and it automatically retracts inside the knife handle. The knife can be locked temporarily by moving a small knob on the back of the handle, it prevents accidental protraction of the knife blade. Knife can be locked permanently by pulling the base of the handle backwards. Once it is locked permanently, it can't be released without breaking the handle completely.
    Type: Application
    Filed: October 4, 2005
    Publication date: April 5, 2007
    Inventor: Gajendra Singh
  • Patent number: 7107475
    Abstract: A digital delay locked loop uses a delay array to delay an input signal by an amount indicated by a delay code. A phase of the resulting delayed signal is compared to a corresponding phase of the input signal, and dependent on the comparison, the delay code is updated to indicate whether the delay array needs to provide more delay or less delay. The digital delay locked loop also uses a detection circuit that monitors for a predetermined condition of the delay code. In response to detection of the predetermined condition, the delay code is automatically reset to a value different than a value of the delay code present at a previous reset or initial startup of the digital delay locked loop.
    Type: Grant
    Filed: October 21, 2003
    Date of Patent: September 12, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Brian Amick, Dong Joon Yoon, Tri Tran, Gajendra Singh, Aparna Ramachandran, Claude Gauthier
  • Publication number: 20050288341
    Abstract: Novel diphenyl ether derivatives are provided that exhibit activity useful for reducing glucose, cholesterol, and/or triglyceride levels in plasma, and for treatment of obesity, inflammation, immunological diseases, autoimmune diseases, diabetes and disorders associated with insulin resistance.
    Type: Application
    Filed: March 31, 2005
    Publication date: December 29, 2005
    Inventors: Bishwajit Nag, Abhijeet Nag, Debendranath Dey, Shiv Agarwal, Partha Neogi, Gaddam Reddy, Sangamesh Badiger, Gajendra Singh, Surendra Pandey, Santhanagopalan Chithra
  • Publication number: 20050203102
    Abstract: The present invention provides novel compounds of the general formula (I) and their pharmaceutically acceptable salts. The present invention more particularly provides novel oxazolidinone derivatives of the general formula (I).
    Type: Application
    Filed: March 9, 2005
    Publication date: September 15, 2005
    Applicant: ORCHID CHEMICALS & PHARMACEUTICALS LTD.
    Inventors: Shiv Agarwal, Surendrakumar Pandey, Gajendra Singh, Santhanagopalan Chithra, Matte Samuel
  • Patent number: 6707721
    Abstract: A register file design having an asymmetric bit line driver is provided. More specifically, the register file design uses a memory element that has a footer device that facilitates the discharge/charging of a bit line through a pass device, where a width of the footer device is greater than a width of the pass device. Further, a method for performing low power memory operations using asymmetric bit line drivers is provided.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: March 16, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Gajendra Singh, Aparna Ramachandran, Miao Rao, Shree Kant
  • Publication number: 20030174535
    Abstract: A register file design having an asymmetric bit line driver is provided. More specifically, the register file design uses a memory element that has a footer device that facilitates the discharge/charging of a bit line through a pass device, where a width of the footer device is greater than a width of the pass device. Further, a method for performing low power memory operations using asymmetric bit line drivers is provided.
    Type: Application
    Filed: March 13, 2002
    Publication date: September 18, 2003
    Inventors: Gajendra Singh, Aparna Ramachandran, Miao Rao, Shree Kant