Patents by Inventor Ganesh Balakrishnan

Ganesh Balakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240134795
    Abstract: A method includes, in a cache directory, storing an entry associating a memory region with an exclusive coherency state, and in response to a memory access directed to the memory region, transmitting a demote superprobe to convert at least one cache line of the memory region from an exclusive coherency state to a shared coherency state.
    Type: Application
    Filed: October 18, 2022
    Publication date: April 25, 2024
    Inventors: Ganesh Balakrishnan, Amit Apte, Ann Ling, Vydhyanathan Kalyanasundharam
  • Patent number: 11954033
    Abstract: A method includes, in a cache directory, storing an entry associating a memory region with an exclusive coherency state, and in response to a memory access directed to the memory region, transmitting a demote superprobe to convert at least one cache line of the memory region from an exclusive coherency state to a shared coherency state.
    Type: Grant
    Filed: October 19, 2022
    Date of Patent: April 9, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ganesh Balakrishnan, Amit Apte, Ann Ling, Vydhyanathan Kalyanasundharam
  • Publication number: 20240111683
    Abstract: A method includes, in a cache directory, storing a set of entries corresponding to one or more memory regions having a first region size when the cache directory is in a first configuration, and based on a workload sparsity metric, reconfiguring the cache directory to a second configuration. In the second configuration, each entry in the set of entries corresponds to a memory region having a second region size.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Amit Apte, Ganesh Balakrishnan
  • Patent number: 11874783
    Abstract: A coherent memory fabric includes a plurality of coherent master controllers and a coherent slave controller. The plurality of coherent master controllers each include a response data buffer. The coherent slave controller is coupled to the plurality of coherent master controllers. The coherent slave controller, responsive to determining a selected coherent block read command is guaranteed to have only one data response, sends a target request globally ordered message to the selected coherent master controller and transmits responsive data. The selected coherent master controller, responsive to receiving the target request globally ordered message, blocks any coherent probes to an address associated with the selected coherent block read command until receipt of the responsive data is acknowledged by a requesting client.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: January 16, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Vydhyanathan Kalyanasundharam, Amit P. Apte, Eric Christopher Morton, Ganesh Balakrishnan, Ann M. Ling
  • Patent number: 11874774
    Abstract: A method includes, in response to each write request of a plurality of write requests received at a memory-side cache device coupled with a memory device, writing payload data specified by the write request to the memory-side cache device, and when a first bandwidth availability condition is satisfied, performing a cache write-through by writing the payload data to the memory device, and recording an indication that the payload data written to the memory-side cache device matches the payload data written to the memory device.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: January 16, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ravindra N. Bhargava, Ganesh Balakrishnan, Joe Sargunaraj, Chintan S. Patel, Girish Balaiah Aswathaiya, Vydhyanathan Kalyanasundharam
  • Publication number: 20230402764
    Abstract: The realization of arrays of antennas for specific applications through the use of diffraction optics to create patterns that will allow for parallel writing of arrays.
    Type: Application
    Filed: June 8, 2023
    Publication date: December 14, 2023
    Applicant: UNM Rainforest Innovations
    Inventors: Ganesh Balakrishnan, Christos G. Christodoulou
  • Patent number: 11809322
    Abstract: Systems, apparatuses, and methods for maintaining a region-based cache directory are disclosed. A system includes multiple processing nodes, with each processing node including a cache subsystem. The system also includes a cache directory to help manage cache coherency among the different cache subsystems of the system. In order to reduce the number of entries in the cache directory, the cache directory tracks coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Accordingly, the system includes a region-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the system. The cache directory includes a reference count in each entry to track the aggregate number of cache lines that are cached per region. If a reference count of a given entry goes to zero, the cache directory reclaims the given entry.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: November 7, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Vydhyanathan Kalyanasundharam, Kevin M. Lepak, Amit P. Apte, Ganesh Balakrishnan, Eric Christopher Morton, Elizabeth M. Cooper, Ravindra N. Bhargava
  • Patent number: 11803470
    Abstract: Disclosed are examples of a system and method to communicate cache line eviction data from a CPU subsystem to a home node over a prioritized channel and to release the cache subsystem early to process other transactions.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: October 31, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Amit Apte, Ganesh Balakrishnan, Ann Ling, Vydhyanathan Kalyanasundharam
  • Patent number: 11782848
    Abstract: Systems, apparatuses, and methods for implementing a speculative probe mechanism are disclosed. A system includes at least multiple processing nodes, a probe filter, and a coherent slave. The coherent slave includes an early probe cache to cache recent lookups to the probe filter. The early probe cache includes entries for regions of memory, wherein a region includes a plurality of cache lines. The coherent slave performs parallel lookups to the probe filter and the early probe cache responsive to receiving a memory request. An early probe is sent to a first processing node responsive to determining that a lookup to the early probe cache hits on a first entry identifying the first processing node as an owner of a first region targeted by the memory request and responsive to determining that a confidence indicator of the first entry is greater than a threshold.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: October 10, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Amit P. Apte, Ganesh Balakrishnan, Vydhyanathan Kalyanasundharam, Kevin M. Lepak
  • Patent number: 11748674
    Abstract: A system and method for managing large numbers of computing devices such as cryptocurrency miners in a data center are disclosed. Status values from the computing devices are read and stored into a database, and a Gini coefficient is calculated on a subset of the stored status values. Coefficients beyond a predetermined threshold cause a support ticket to be generated if a support ticket has not already been generated and if the coefficients are not otherwise non-indicative of actual or likely computing device failures.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: September 5, 2023
    Assignee: Core Scientific Operating Company
    Inventors: Ganesh Balakrishnan, Carla Cortez, Aaron Strachan
  • Publication number: 20230195662
    Abstract: A coherent memory fabric includes a plurality of coherent master controllers and a coherent slave controller. The plurality of coherent master controllers each include a response data buffer. The coherent slave controller is coupled to the plurality of coherent master controllers. The coherent slave controller, responsive to determining a selected coherent block read command is guaranteed to have only one data response, sends a target request globally ordered message to the selected coherent master controller and transmits responsive data. The selected coherent master controller, responsive to receiving the target request globally ordered message, blocks any coherent probes to an address associated with the selected coherent block read command until receipt of the responsive data is acknowledged by a requesting client.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Vydhyanathan Kalyanasundharam, Amit P. Apte, Eric Christopher Morton, Ganesh Balakrishnan, Ann M. Ling
  • Publication number: 20230195632
    Abstract: A data processing system includes a plurality of coherent masters, a plurality of coherent slaves, and a coherent data fabric. The coherent data fabric has upstream ports coupled to the plurality of coherent masters and downstream ports coupled to the plurality of coherent slaves for selectively routing accesses therebetween. The coherent data fabric includes a probe filter and a directory cleaner. The probe filter is associated with at least one of the downstream ports and has a plurality of entries that store information about each entry. The directory cleaner periodically scans the probe filter and selectively removes a first entry from the probe filter after the first entry is scanned.
    Type: Application
    Filed: December 20, 2021
    Publication date: June 22, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Amit P. Apte, Kevin Michael Lepak, Ganesh Balakrishnan, Vydhyanathan Kalyanasundharam
  • Patent number: 11669901
    Abstract: A communication network may include a first computer and a second computer configured for communication with each other. The second computer may include a project manager module configured to receive computing projects from the first computer and manage the execution of work tasks for the computing projects. The project manager may throttle performance if needed to prevent negative impact on the performance of other applications also being executed on the second computer, such as a video game. Rewards for performing the work tasks may be automatically converted from a first cryptocurrency to a second currency such as a video game currency.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: June 6, 2023
    Assignee: CORE SCIENTIFIC OPERATING COMPANY
    Inventor: Ganesh Balakrishnan
  • Patent number: 11567821
    Abstract: Systems and methods for reporting health status for a plurality of computing devices such as within a data center are disclosed. A management device connected to the computing devices via a network executes a management application that periodically requests and receives status data from the computing devices. A pool checker may be used to track corresponding pool status data, and an environment checker may periodically request and receive environmental data from environmental sensors for temperature, humidity, and audio. A report generator creates health reports and assigns device health classifications based on the device status data, the environmental data, and the pool health data. The data may be associated with one or more locations and customers, permitting filtering of the report.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: January 31, 2023
    Assignee: Core Scientific Operating Company
    Inventors: Kristy-Leigh Anne Minehan, Ganesh Balakrishnan, Evan Adams, Carla Cortez, Ian Ferreira
  • Publication number: 20230021897
    Abstract: A method for managing a plurality of computing devices comprises: periodically collecting status information from the plurality of computing devices; providing a user interface including: a first control to select one or more of the plurality of computing devices; and a second control to select one of a plurality of operating modes, the plurality of operating modes including: a manual mode in which the one or more selected computing devices are operated according to user selected settings; and an intelligent mode in which the one or more selected computing devices are operated according to dynamic settings; and in response to one or more of the plurality of computing devices being selected with the first control and one of the plurality of operating modes being selected with the second control, applying the selected operating mode to the one or more selected computing devices.
    Type: Application
    Filed: September 27, 2022
    Publication date: January 26, 2023
    Inventors: Ganesh Balakrishnan, Kristy-Leigh Minehan, Evan Adams, Gabrielle Gordon
  • Patent number: 11507517
    Abstract: Disclosed is a cache directory including one or more cache directories configurable to interchange within each cache directory entry at least one bit between a first field and a second field to change the size of the region of memory represented and the number of cache lines tracked in the cache subsystem.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: November 22, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Amit Apte, Ganesh Balakrishnan
  • Patent number: 11489736
    Abstract: A system and method for easily managing a data center with multiple computing devices such as cryptocurrency miners from different manufactures is disclosed. A first computer includes a management application to manage the selected computing devices and periodically read and store status information from them into a database. Controls are presented to enable selection of one or more of the devices and to apply an operating mode, including manual, semi-automatic, automatic, and intelligent modes. Machine learning may be used to determine recommended settings for the selected set of computing devices.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: November 1, 2022
    Assignee: Core Scientific, Inc.
    Inventors: Ganesh Balakrishnan, Kristy-Leigh Minehan, Evan Adams, Gabrielle Gordon
  • Publication number: 20220237117
    Abstract: Systems, apparatuses, and methods for maintaining region-based cache directories split between node and memory are disclosed. The system with multiple processing nodes includes cache directories split between the nodes and memory to help manage cache coherency among the nodes' cache subsystems. In order to reduce the number of entries in the cache directories, the cache directories track coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Each processing node includes a node-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the node. The node-based cache directory includes a reference count field in each entry to track the aggregate number of cache lines that are cached per region. The memory-based cache directory includes entries for regions which have an entry stored in any node-based cache directory of the system.
    Type: Application
    Filed: April 15, 2022
    Publication date: July 28, 2022
    Inventors: Vydhyanathan Kalyanasundharam, Kevin M. Lepak, Amit P. Apte, Ganesh Balakrishnan
  • Patent number: 11314646
    Abstract: Systems, apparatuses, and methods for maintaining region-based cache directories split between node and memory are disclosed. The system with multiple processing nodes includes cache directories split between the nodes and memory to help manage cache coherency among the nodes' cache subsystems. In order to reduce the number of entries in the cache directories, the cache directories track coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Each processing node includes a node-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the node. The node-based cache directory includes a reference count field in each entry to track the aggregate number of cache lines that are cached per region. The memory-based cache directory includes entries for regions which have an entry stored in any node-based cache directory of the system.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: April 26, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Vydhyanathan Kalyanasundharam, Kevin M. Lepak, Amit P. Apte, Ganesh Balakrishnan
  • Publication number: 20220100672
    Abstract: Disclosed is a cache directory including one or more cache directories configurable to interchange within each cache directory entry at least one bit between a first field and a second field to change the size of the region of memory represented and the number of cache lines tracked in the cache subsystem.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Inventors: Amit Apte, Ganesh Balakrishnan