Patents by Inventor Ganesh Balakrishnan

Ganesh Balakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11119926
    Abstract: Systems, apparatuses, and methods for maintaining a region-based cache directory are disclosed. A system includes multiple processing nodes, with each processing node including a cache subsystem. The system also includes a cache directory to help manage cache coherency among the different cache subsystems of the system. In order to reduce the number of entries in the cache directory, the cache directory tracks coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Accordingly, the system includes a region-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the system. The cache directory includes a reference count in each entry to track the aggregate number of cache lines that are cached per region. If a reference count of a given entry goes to zero, the cache directory reclaims the given entry.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: September 14, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Vydhyanathan Kalyanasundharam, Kevin M. Lepak, Amit P. Apte, Ganesh Balakrishnan, Eric Christopher Morton, Elizabeth M. Cooper, Ravindra N. Bhargava
  • Publication number: 20210064545
    Abstract: Systems, apparatuses, and methods for implementing a speculative probe mechanism are disclosed. A system includes at least multiple processing nodes, a probe filter, and a coherent slave. The coherent slave includes an early probe cache to cache recent lookups to the probe filter. The early probe cache includes entries for regions of memory, wherein a region includes a plurality of cache lines. The coherent slave performs parallel lookups to the probe filter and the early probe cache responsive to receiving a memory request. An early probe is sent to a first processing node responsive to determining that a lookup to the early probe cache hits on a first entry identifying the first processing node as an owner of a first region targeted by the memory request and responsive to determining that a confidence indicator of the first entry is greater than a threshold.
    Type: Application
    Filed: September 14, 2020
    Publication date: March 4, 2021
    Inventors: Amit P. Apte, Ganesh Balakrishnan, Vydhyanathan Kalyanasundharam, Kevin M. Lepak
  • Patent number: 10922237
    Abstract: Systems, apparatuses, and methods for accelerating accesses to private regions in a region-based cache directory scheme are disclosed. A system includes multiple processing nodes, one or more memory devices, and one or more region-based cache directories to manage cache coherence among the nodes' cache subsystems. Region-based cache directories track coherence on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. The cache directory entries for regions that are only accessed by a single node are cached locally at the node. Updates to the reference count for these entries are made locally rather than sending updates to the cache directory. When a second node accesses a first node's private region, the region is now considered shared, and the entry for this region is transferred from the first node back to the cache directory.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: February 16, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Vydhyanathan Kalyanasundharam, Amit P. Apte, Ganesh Balakrishnan
  • Publication number: 20210028983
    Abstract: A system and method for easily managing a data center with multiple computing devices such as cryptocurrency miners from different manufactures is disclosed. A first computer includes a management application to manage the selected computing devices and periodically read and store status information from them into a database. Controls are presented to enable selection of one or more of the devices and to apply an operating mode, including manual, semi-automatic, automatic, and intelligent modes. Machine learning may be used to determine recommended settings for the selected set of computing devices.
    Type: Application
    Filed: December 9, 2019
    Publication date: January 28, 2021
    Inventor: Ganesh Balakrishnan
  • Publication number: 20210026729
    Abstract: A management device for managing a plurality of computing devices in a data center may comprise a network interface, a first module that periodically sends health status queries to the computing devices via the network interface, a second module configured to receive responses to the health status queries and collect and store health status data for the computing devices, a third module configured to create support tickets, and/or a fourth module configured to (i) create and periodically update a Cox proportional hazards (CPH) model based on the health status data; (ii) apply a deep neural network (DNN) to the input of the CPH model; (iii) determine a probability of failure for each computing device; (iv) compare each probability of failure with a threshold; and (v) cause the third module to generate a pre-failure support ticket for each computing device having determined probabilities of failure above the threshold.
    Type: Application
    Filed: May 20, 2020
    Publication date: January 28, 2021
    Inventors: Ian Ferreira, Ganesh Balakrishnan, Evan Adams, Carla Cortez, Eric Hullander
  • Publication number: 20210028999
    Abstract: A system and method for managing large numbers of computing devices such as cryptocurrency miners in a data center are disclosed. A three-dimensional (3D) model of the data center is created using machine-readable codes. The 3D model includes device and bin location information. Status data is captured from the computing devices, associated with location, stored in a database, and used to populate the 3D model, which is rendered in various two-dimensional and 3D views to provide the user with information helpful in managing the data center.
    Type: Application
    Filed: December 9, 2019
    Publication date: January 28, 2021
    Inventors: Ganesh Balakrishnan, Thomas Fuller, Chandra Ponneganti
  • Publication number: 20210026727
    Abstract: Systems and methods for reporting health status for a plurality of computing devices such as within a data center are disclosed. A management device connected to the computing devices via a network executes a management application that periodically requests and receives status data from the computing devices. A pool checker may be used to track corresponding pool status data, and an environment checker may periodically request and receive environmental data from environmental sensors for temperature, humidity, and audio. A report generator creates health reports and assigns device health classifications based on the device status data, the environmental data, and the pool health data. The data may be associated with one or more locations and customers, permitting filtering of the report.
    Type: Application
    Filed: July 22, 2020
    Publication date: January 28, 2021
    Inventors: Kristy-Leigh Anne Minehan, Ganesh Balakrishnan, Evan Adams, Carla Cortez, Ian Ferreira
  • Publication number: 20210027221
    Abstract: A system and method for managing large numbers of computing devices such as cryptocurrency miners in a data center are disclosed. Status values from the computing devices are read and stored into a database, and a Gini coefficient is calculated on a subset of the stored status values. Coefficients beyond a predetermined threshold cause a support ticket to be generated if a support ticket has not already been generated and if the coefficients are not otherwise non-indicative of actual or likely computing device failures.
    Type: Application
    Filed: December 9, 2019
    Publication date: January 28, 2021
    Inventors: Ganesh Balakrishnan, Carla Cortez, Aaron Strachan
  • Publication number: 20210012420
    Abstract: A communication network may include a first computer and a second computer configured for communication with each other. The second computer may include a project manager module configured to receive computing projects from the first computer and manage the execution of work tasks for the computing projects. The project manager may throttle performance if needed to prevent negative impact on the performance of other applications also being executed on the second computer, such as a video game. Rewards for performing the work tasks may be automatically converted from a first cryptocurrency to a second currency such as a video game currency.
    Type: Application
    Filed: April 6, 2020
    Publication date: January 14, 2021
    Inventor: Ganesh Balakrishnan
  • Publication number: 20200401519
    Abstract: Systems, apparatuses, and methods for maintaining region-based cache directories split between node and memory are disclosed. The system with multiple processing nodes includes cache directories split between the nodes and memory to help manage cache coherency among the nodes' cache subsystems. In order to reduce the number of entries in the cache directories, the cache directories track coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Each processing node includes a node-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the node. The node-based cache directory includes a reference count field in each entry to track the aggregate number of cache lines that are cached per region. The memory-based cache directory includes entries for regions which have an entry stored in any node-based cache directory of the system.
    Type: Application
    Filed: July 2, 2020
    Publication date: December 24, 2020
    Inventors: Vydhyanathan Kalyanasundharam, Kevin M. Lepak, Amit P. Apte, Ganesh Balakrishnan
  • Patent number: 10824953
    Abstract: Various implementations of a method, system, and computer program product for pattern matching using a reconfigurable array processor are disclosed. In one embodiment, a processor array manager of the reconfigurable array processor receives an input data stream for pattern matching and generates a tokenized input data stream from the input data stream. A different portion of the tokenized input data stream is provided to each of a plurality of processing elements of the reconfigurable array processor. Each processing element can compare the received portion of the tokenized input data stream against one or more reference patterns to generate an intermediate result that indicates whether the portion of the tokenized input data stream matches a reference pattern. The processor array manager can combine the intermediate results received from each processing element to yield a final result that indicates whether the input data stream includes a reference pattern.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: November 3, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bulent Abali, Ganesh Balakrishnan, Bartholomew Blaner, Peter A. Sandon, Jeffrey A. Stuecheli
  • Patent number: 10824952
    Abstract: Various implementations of a method, system, and computer program product for pattern matching using a reconfigurable array processor are disclosed. In one embodiment, a processor array manager of the reconfigurable array processor receives an input data stream for pattern matching and generates a tokenized input data stream from the input data stream. A different portion of the tokenized input data stream is provided to each of a plurality of processing elements of the reconfigurable array processor. Each processing element can compare the received portion of the tokenized input data stream against one or more reference patterns to generate an intermediate result that indicates whether the portion of the tokenized input data stream matches a reference pattern. The processor array manager can combine the intermediate results received from each processing element to yield a final result that indicates whether the input data stream includes a reference pattern.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: November 3, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bulent Abali, Ganesh Balakrishnan, Bartholomew Blaner, Peter A. Sandon, Jeffrey A. Stuecheli
  • Patent number: 10824585
    Abstract: An array processor includes a managing element having a load streaming unit coupled to multiple processing elements. The load streaming unit provides input data portions to each of a first subset of the processing elements and also receives output data from each of a second subset of the processing elements based on a comparatively sorted combination of the input data portions provided to the first subset of processing elements. Furthermore, each of processing elements is configurable by the managing element to compare input data portions received from either the load streaming unit or two or more of the other processing elements, wherein the input data portions are stored for processing in respective queues. Each processing unit is further configurable to select an input data portion to be output data based on the comparison, and in response to selecting the input data portion, remove a queue entry corresponding to the selected input data portion.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: November 3, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ganesh Balakrishnan, Bartholomew Blaner, John J. Reilly, Jeffrey A. Stuecheli
  • Patent number: 10776282
    Abstract: Systems, apparatuses, and methods for implementing a speculative probe mechanism are disclosed. A system includes at least multiple processing nodes, a probe filter, and a coherent slave. The coherent slave includes an early probe cache to cache recent lookups to the probe filter. The early probe cache includes entries for regions of memory, wherein a region includes a plurality of cache lines. The coherent slave performs parallel lookups to the probe filter and the early probe cache responsive to receiving a memory request. An early probe is sent to a first processing node responsive to determining that a lookup to the early probe cache hits on a first entry identifying the first processing node as an owner of a first region targeted by the memory request and responsive to determining that a confidence indicator of the first entry is greater than a threshold.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: September 15, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Amit P. Apte, Ganesh Balakrishnan, Vydhyanathan Kalyanasundharam, Kevin M. Lepak
  • Patent number: 10705959
    Abstract: Systems, apparatuses, and methods for maintaining region-based cache directories split between node and memory are disclosed. The system with multiple processing nodes includes cache directories split between the nodes and memory to help manage cache coherency among the nodes' cache subsystems. In order to reduce the number of entries in the cache directories, the cache directories track coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Each processing node includes a node-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the node. The node-based cache directory includes a reference count field in each entry to track the aggregate number of cache lines that are cached per region. The memory-based cache directory includes entries for regions which have an entry stored in any node-based cache directory of the system.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: July 7, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Vydhyanathan Kalyanasundharam, Kevin M. Lepak, Amit P. Apte, Ganesh Balakrishnan
  • Patent number: 10691528
    Abstract: A system and method for automating management and repair of a plurality of computing devices located in a data center is disclosed. Health status queries are issued for one or more of the computing devices. If responses not indicative of good device health are received, one or more repair instructions are automatically sent to the unhealthy computing device to repair the computing device by moving it to an acceptable state. If the repair instructions are not successful, a support ticket is automatically generated for the corresponding computing device or devices. Problematic statuses across areas of the data center may be detected and ticketed in addition to individual problematic devices. So-called repeat offender devices may be detected and ticketed even if the repair instructions are successful.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: June 23, 2020
    Assignee: Core Scientific, Inc.
    Inventors: Ian Ferreira, Ganesh Balakrishnan, Evan Adams, Carla Cortez, Eric Hullander
  • Patent number: 10680892
    Abstract: Aspects of an embodiment of the invention disclose a method, computer program product, and system for managing the energy efficiency of servers providing multi-class computing services with Quality of Service (QoS) assurance. Computing resources are clustered into at least three groups, where each group has a separate power management policy (PMP). A plurality of requests are received from a plurality of devices, and are sorted into at least three service classes based on the requests' QoS criteria. Each request is assigned to one of at least three service queues based on the request's service class, and each service group is processed by a group of computing resources. The power management policies are configured such that each group of computing resources may service requests at an energy efficient point while meeting the QoS criteria of the service class.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: June 9, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ganesh Balakrishnan, Mohammad Peyravian, Srinivasan Ramani, Brian M. Rogers, Ken V. Vu
  • Publication number: 20200081844
    Abstract: Systems, apparatuses, and methods for accelerating accesses to private regions in a region-based cache directory scheme are disclosed. A system includes multiple processing nodes, one or more memory devices, and one or more region-based cache directories to manage cache coherence among the nodes' cache subsystems. Region-based cache directories track coherence on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. The cache directory entries for regions that are only accessed by a single node are cached locally at the node. Updates to the reference count for these entries are made locally rather than sending updates to the cache directory. When a second node accesses a first node's private region, the region is now considered shared, and the entry for this region is transferred from the first node back to the cache directory.
    Type: Application
    Filed: September 12, 2018
    Publication date: March 12, 2020
    Inventors: Vydhyanathan Kalyanasundharam, Amit P. Apte, Ganesh Balakrishnan
  • Publication number: 20200073801
    Abstract: Systems, apparatuses, and methods for maintaining region-based cache directories split between node and memory are disclosed. The system with multiple processing nodes includes cache directories split between the nodes and memory to help manage cache coherency among the nodes' cache subsystems. In order to reduce the number of entries in the cache directories, the cache directories track coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Each processing node includes a node-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the node. The node-based cache directory includes a reference count field in each entry to track the aggregate number of cache lines that are cached per region. The memory-based cache directory includes entries for regions which have an entry stored in any node-based cache directory of the system.
    Type: Application
    Filed: August 31, 2018
    Publication date: March 5, 2020
    Inventors: Vydhyanathan Kalyanasundharam, Kevin M. Lepak, Amit P. Apte, Ganesh Balakrishnan
  • Patent number: 10572389
    Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. External system memory is used as a last-level cache and includes one of a variety of types of dynamic random access memory (DRAM). A memory controller generates a tag request and a separate data request based on a same, single received memory request. The sending of the tag request is prioritized over sending the data request. A partial tag comparison is performed during processing of the tag request. If a tag miss is detected for the partial tag comparison, then the data request is cancelled, and the memory request is sent to main memory. If one or more tag hits are detected for the partial tag comparison, then processing of the data request is dependent upon the result of the full tag comparison.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: February 25, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ravindra N. Bhargava, Ganesh Balakrishnan