Patents by Inventor Ganesh Balasubramanian

Ganesh Balasubramanian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250149373
    Abstract: Semiconductor components and systems having substrate contacting surfaces with a reduced hardness are provided. Systems and components include a ceramic, metallic, or non-metallic component for contacting a substrate. Systems and components include a layer of coating material on at least a portion of a substrate contacting surface of the component. Systems and components include where the component for contacting a substrate includes a component Vickers hardness value, and the layer of coating material exhibits a coating layer Vickers hardness value. Systems and components include where the coating layer Vickers hardness value is greater than or about 10% less than the component Vickers hardness value.
    Type: Application
    Filed: December 19, 2023
    Publication date: May 8, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Nitin Deepak, Jennifer Sun, Mayur Govind Kulkarni, Miguel S. Fung, Darius "D" Alexander-Jones, Chih Peng, Deenesh Padhi, Kwangduk Douglas Lee, Ganesh Balasubramanian, Juan Carlos Rocha-Alvarez, Simmon Kuo, Nagarajan Rajagopalan, Shankho Sen
  • Publication number: 20250125180
    Abstract: Substrate support assemblies may include an electrostatic chuck body defining a substrate support surface that defines a substrate seat. Assemblies may include a support stem coupled with the electrostatic chuck body. Assemblies may include a first bipolar electrode embedded within the electrostatic chuck body. Assemblies may include a second bipolar electrode embedded within the electrostatic chuck body radially inward of at least a portion of the first bipolar electrode and coaxial with the first bipolar electrode. Assemblies may include an annular electrode disposed about the first bipolar electrode, where the annular electrode is DC floated and RF powered and exhibits an induced DC current.
    Type: Application
    Filed: October 11, 2023
    Publication date: April 17, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Jian Li, Deenesh Padhi, Abhishek Kumar Verma, Kallol Bera, Juan Carlos Rocha-Alvarez, Wenhao Zhang, Ganesh Balasubramanian
  • Publication number: 20250118578
    Abstract: Exemplary substrate support assemblies may include a support plate that comprises a substrate support surface. The assemblies may include a support stem coupled with the support plate. A channel may be defined through at least a portion of a length of the support stem and extends through the substrate support surface. A temperature sensor assembly may be disposed within the channel. The temperature sensor assembly may include a light pipe disposed within the channel such that a top end of the light pipe extending through at least a portion of the support plate. The temperature sensor assembly may include a sensor that is coupled with a bottom end of the light pipe.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 10, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Ajith Karonnan Ramapurath, Jian Li, Ganesh Balasubramanian, Juan Carlos Rocha-Alvarez
  • Publication number: 20250116001
    Abstract: A semiconductor processing chamber may include a pedestal configured to support a substrate during a plasma-enhanced chemical-vapor deposition (PECVD) process that forms a film on a surface of the substrate. The chamber may also include one or more internal meshes embedded in the pedestal. The one or more internal meshes may be configured to deliver radio-frequency (RF) power to a plasma in the semiconductor processing chamber during the PECVD process. An outer diameter of the one or more internal meshes may be less that a diameter of the substrate. The chamber may further include an RF source configured to deliver the RF power to the one more internal meshes. This configuration may reduce arcing within the processing chamber.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 10, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Allison Yau, Manoj Kumar Jana, Wen-Shan Lin, Zhiling Dun, Xinhai Han, Deenesh Padhi, Jian Li, Yuanchang Chen, Wenhao Zhang, Edward P. Hammond, Alexander V. Garachtchenko, Ganesh Balasubramanian, Juan Carlos Rocha-Alvarez, Sathya Ganta
  • Publication number: 20250060321
    Abstract: Disclosed are systems and techniques for fast and efficient detection of defects in wafers, including a system that has a factory interface (FI) coupled to a wafer carrier and a load lock chamber. The FI includes a robot fetches a wafer from the wafer carrier and deliver the first wafer to an aligner device. The aligner device imparts rotational motion to the wafer and identifies, using the rotational motion of the wafer, a position of a reference feature of the wafer. The FI further includes an optical inspection system that collects, during the rotational motion imparted to the wafer, an imaging data for the first wafer. The system further includes a processing device that performs evaluation, using the imaging data, of a presence of defect(s) in the wafer, and evaluates suitability of the wafer for wafer processing.
    Type: Application
    Filed: August 16, 2023
    Publication date: February 20, 2025
    Inventors: Elias Anthony Martinez, Sidharth Bhatia, Sarah Michelle Bobek, Ka Shun Wong, Zhi Wang, Martin J. Seamons, Raj Singu, Abdul Aziz Khaja, Ganesh Balasubramanian, Mark McTaggart Wylie
  • Patent number: 12211908
    Abstract: Exemplary semiconductor structures and processing methods may include forming a first portion of a first semiconductor layer characterized by a first etch rate for an etch treatment, forming a second portion of the first semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment, and forming a third portion of the first semiconductor layer characterized by a third etch rate that is greater than the second etch rate. The processing methods may further include etching an opening through the first semiconductor layer, where the opening has a height and a width, and where the opening is characterized by a variation in the width between a midpoint of the height of the opening and an endpoint of the opening that is less than or about 5 ?.
    Type: Grant
    Filed: September 1, 2023
    Date of Patent: January 28, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Akhil Singhal, Allison Yau, Sang-Jin Kim, Zeqiong Zhao, Zhijun Jiang, Deenesh Padhi, Ganesh Balasubramanian
  • Publication number: 20240387190
    Abstract: Exemplary methods of semiconductor processing may include providing deposition precursors to a processing region of a semiconductor processing chamber. The deposition precursors may include a silicon-containing precursor and a metal-containing precursor. The silicon-containing precursor and the metal-containing precursor may be fluidly isolated prior to reaching the processing region. A substrate may be housed within the processing region. The methods may include generating plasma effluents of the deposition precursors. The methods may include forming a layer of silicon-and-metal-containing material on the substrate.
    Type: Application
    Filed: May 15, 2023
    Publication date: November 21, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Guangyan Zhong, Jongbeom Seo, Eswaranand Venkatasubramanian, Santhosh Kiran Rajarajan, Diwakar Kedlaya, Ganesh Balasubramanian, Abhijit Basu Mallick
  • Publication number: 20240387174
    Abstract: Exemplary methods of semiconductor processing may include providing deposition precursors to a processing region of a semiconductor processing chamber. The deposition precursors may include a silicon-and-halogen-containing precursor and a metal-containing precursor. A substrate may be housed within the processing region. The methods may include generating plasma effluents of the deposition precursors. The methods may include forming a layer of silicon-and-metal-containing material on the substrate.
    Type: Application
    Filed: May 15, 2023
    Publication date: November 21, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Guangyan Zhong, Eswaranand Venkatasubramanian, Rui Cheng, Santhosh Kiran Rajarajan, Ganesh Balasubramanian, Abhijit Basu Mallick, Karthik Janakiraman, Guoqing Li
  • Patent number: 12106958
    Abstract: Embodiments of the present disclosure generally relate to methods for cleaning a chamber comprising introducing a gas to a processing volume of the chamber, providing a first radiofrequency (RF) power having a first frequency of about 40 MHz or greater to a lid of the chamber, providing a second RF power having a second frequency to an electrode disposed in a substrate support within the processing volume, and removing at least a portion of a film disposed on a surface of a chamber component of the chamber. The second frequency is about 10 MHz to about 20 MHz.
    Type: Grant
    Filed: June 27, 2023
    Date of Patent: October 1, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Anup Kumar Singh, Rick Kustra, Vinayak Vishwanath Hassan, Bhaskar Kumar, Krishna Nittala, Pramit Manna, Kaushik Alayavalli, Ganesh Balasubramanian
  • Patent number: 12094689
    Abstract: Exemplary semiconductor processing systems may include a processing chamber including a lid stack having an output manifold. The systems may include a gas panel. The systems may include an input manifold. The input manifold may fluidly couple the gas panel with the output manifold of the processing chamber. A delivery line may extend from the input manifold to the output manifold. The systems may include a first transmission line extending from a first set of precursor sources of the gas panel to the delivery line. The systems may include a second transmission line extending from a second set of precursor sources of the gas panel to the delivery line. The second transmission line may be switchably coupled between the delivery line and an exhaust of the semiconductor processing system.
    Type: Grant
    Filed: July 19, 2020
    Date of Patent: September 17, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Sai Susmita Addepalli, Yue Chen, Abhigyan Keshri, Qiang Ma, Zhijun Jiang, Shailendra Srivastava, Daemian Raj Benjamin Raj, Ganesh Balasubramanian
  • Patent number: 12031416
    Abstract: A tool includes a mandrel and at least one gate. The mandrel includes a bore, and the mandrel is able to connect in-line with at least one sand control device of a bottom hole assembly such that the mandrel is coaxial with the at least one sand control device. The mandrel also includes a flow path configuration, such as, at least one flow path connecting the at least one sand control device to the bore, at least one flow path connecting the bore to at least two sand control devices, and at least one flow path connecting the bore to the at least one sand control device and to another device of the bottom hole assembly. The at least one gate has an initial position, and the at least one gate is configured to move from the initial position into a different position to control fluid flow.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: July 9, 2024
    Assignee: Schlumberger Technology Corporation
    Inventors: Maria Tafur, Ganesh Balasubramanian, Amrendra Kumar, Raghuram Kamath, Benoit Deville, Michael Dean Langlais
  • Patent number: 12020911
    Abstract: The present disclosure relates to methods and systems for chucking in substrate processing chambers. In one implementation, a method of chucking one or more substrates in a substrate processing chamber includes applying a chucking voltage to a pedestal. A substrate is disposed on a support surface of the pedestal. The method also includes ramping the chucking voltage from the applied voltage, detecting an impedance shift while ramping the chucking voltage, determining a corresponding chucking voltage at which the impedance shift occurs, and determining a refined chucking voltage based on the impedance shift and the corresponding chucking voltage.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: June 25, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Bhaskar Kumar, Ganesh Balasubramanian, Vivek Bharat Shah, Jiheng Zhao
  • Patent number: 12002702
    Abstract: Methods and systems of detection of wafer de-chucking in a semiconductor processing chamber are disclosed. Methods and systems of interdiction are also disclosed to prevent hardware and wafer damage during semiconductor fabrication if and when de-chucking is detected. In one embodiment, a de-chucking detection method is based on measuring change in imaginary impedance of a plasma circuit, along with measuring one or both of reflected RF power and arc count. In another embodiment, a possibility of imminent de-chucking is detected even before complete de-chucking occurs by analyzing the signature change in imaginary impedance.
    Type: Grant
    Filed: September 1, 2022
    Date of Patent: June 4, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Ganesh Balasubramanian, Byung Chul Yoon, Hemant Mungekar
  • Publication number: 20240052730
    Abstract: Electrical gas lift valves and systems including electrical gas lift valves are provided.
    Type: Application
    Filed: February 9, 2022
    Publication date: February 15, 2024
    Inventors: Ganesh Balasubramanian, Oguzhan Guven, Jason Bigelow, Naomi Crawford, Yann Dufour, Maria Tafur, Robert Krush
  • Patent number: 11898249
    Abstract: A method of processing a substrate according to a PECVD process is described. Temperature profile of the substrate is adjusted to change deposition rate profile across the substrate. Plasma density profile is adjusted to change deposition rate profile across the substrate. Chamber surfaces exposed to the plasma are heated to improve plasma density uniformity and reduce formation of low quality deposits on chamber surfaces. In situ metrology may be used to monitor progress of a deposition process and trigger control actions involving substrate temperature profile, plasma density profile, pressure, temperature, and flow of reactants.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: February 13, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Nagarajan Rajagopalan, Xinhai Han, Michael Wenyoung Tsiang, Masaki Ogata, Zhijun Jiang, Juan Carlos Rocha-Alvarez, Thomas Nowak, Jianhua Zhou, Ramprakash Sankarakrishnan, Amit Kumar Bansal, Jeongmin Lee, Todd Egan, Edward W. Budiarto, Dmitriy Panasyuk, Terrance Y. Lee, Jian J. Chen, Mohamad A. Ayoub, Heung Lak Park, Patrick Reilly, Shahid Shaikh, Bok Hoen Kim, Sergey Starik, Ganesh Balasubramanian
  • Patent number: 11894228
    Abstract: Exemplary methods of semiconductor processing may include forming a plasma of a carbon-containing precursor in a processing region of a semiconductor processing chamber. The methods may include depositing a carbon-containing material on a substrate housed in the processing region of the semiconductor processing chamber. The methods may include halting a flow of the carbon-containing precursor into the processing region of the semiconductor processing chamber. The methods may include contacting the carbon-containing material with plasma effluents of an oxidizing material. The methods may include forming volatile materials from a surface of the carbon-containing material.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: February 6, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Sudha S. Rathi, Ganesh Balasubramanian, Nagarajan Rajagopalan, Abdul Aziz Khaja, Prashanthi Para, Hiral D. Tailor
  • Patent number: 11875969
    Abstract: A processing system comprises a chamber body, a substrate support and a lid assembly. The substrate support is located in the chamber body and comprises a first electrode. The lid assembly is positioned over the chamber body and defines a processing volume. The lid assembly comprises a faceplate, a second electrode positioned between the faceplate and the chamber body, and an insulating member positioned between the second electrode and the processing volume. A power supply system is coupled to the first electrode and the faceplate and is configured to generate a plasma in the processing volume.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: January 16, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Fei Wu, Abdul Aziz Khaja, Sungwon Ha, Vinay K. Prabhakar, Ganesh Balasubramanian
  • Publication number: 20240011371
    Abstract: A tool includes a mandrel and at least one gate. The mandrel includes a bore, and the mandrel is able to connect in-line with at least one sand control device of a bottom hole assembly such that the mandrel is coaxial with the at least one sand control device. The mandrel also includes a flow path configuration, such as, at least one flow path connecting the at least one sand control device to the bore, at least one flow path connecting the bore to at least two sand control devices, and at least one flow path connecting the bore to the at least one sand control device and to another device of the bottom hole assembly. The at least one gate has an initial position, and the at least one gate is configured to move from the initial position into a different position to control fluid flow.
    Type: Application
    Filed: October 5, 2021
    Publication date: January 11, 2024
    Inventors: Maria Tafur, Ganesh Balasubramanian, Amrendra Kumar, Raghuram Kamath, Benoit Deville, Michael Dean Langlais
  • Patent number: 11859275
    Abstract: Implementations of the present disclosure generally relate to hardmask films and methods for depositing hardmask films. More particularly, implementations of the present disclosure generally relate to tungsten carbide hardmask films and processes for depositing tungsten carbide hardmask films. In one implementation, a method of forming a tungsten carbide film is provided. The method comprises forming a tungsten carbide initiation layer on a silicon-containing surface of a substrate at a first deposition rate. The method further comprises forming a tungsten carbide film on the tungsten carbide initiation layer at a second deposition rate, wherein the second deposition rate is greater than the first deposition rate.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: January 2, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Vivek Bharat Shah, Anup Kumar Singh, Bhaskar Kumar, Ganesh Balasubramanian
  • Publication number: 20230411462
    Abstract: Exemplary semiconductor structures and processing methods may include forming a first portion of a first semiconductor layer characterized by a first etch rate for an etch treatment, forming a second portion of the first semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment, and forming a third portion of the first semiconductor layer characterized by a third etch rate that is greater than the second etch rate. The processing methods may further include etching an opening through the first semiconductor layer, where the opening has a height and a width, and where the opening is characterized by a variation in the width between a midpoint of the height of the opening and an endpoint of the opening that is less than or about 5 ?.
    Type: Application
    Filed: September 1, 2023
    Publication date: December 21, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Akhil Singhal, Allison Yau, Sang-Jin Kim, Zeqiong Zhao, Zhijun Jiang, Deenesh Padhi, Ganesh Balasubramanian