Abstract: Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.

Abstract: An apparatus, and an associated method, for a device containing a camera module. An ambient light sensor senses ambient light conditions and provides an indication of the sensed conditions to an exposure setter. The exposure setter utilizes the indication of the ambient light conditions in the selection of the initial exposure. Convergence procedures are utilized to converge the exposure settings to a final exposure setting.

Abstract: An apparatus, and an associated method, for facilitating stabilization of a recorded video sequence, formed of captured image frames. Captured image frames are cropped by a frame cropper. Cropping of an image is dependent upon lighting conditions. Upon the occurrence of a low-light, lighting condition, the amount of cropping is altered. And, when acceptable lighting conditions return, the amount of cropping is again altered, all in a manner to facilitate video stabilization.

Abstract: An apparatus, and an associated method, facilitates capturing an image in an electronic camera without having to wait for an image to settle or the camera to stabilize. Image frames are captured continuously. Data representing captured images is compressed. The compressed files are stored continuously, such that even before a shutter button is actuated, one or compressed image frames have already been recorded. When the shutter button is actuated, the largest of the compressed data files is selected for use, such as display, printing or transmission. Selection is made based on the size of the compressed image file.

Abstract: Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.

Abstract: Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.

Abstract: A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.

Abstract: A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.

Abstract: Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.

Abstract: A method and manufacture for charge storage layer separation is provided. A layer, such as a polymer layer, is deposited on top of an ONO layer so that the polymer layer is planarized, or approximately planarized. The ONO includes at least a first region and a second region, where the first region is higher than the second region. For example, the first region may be the portion of the ONO that is over the source/drain region, and the second region may be the portion of the ONO that is over the shallow trench. Etching is performed on the polymer layer to expose the first region of the ONO layer, leaving the second region of the ONO unexposed. The etching continues to occur to etch the exposed ONO at the first region so that the ONO layer is etched away in the first region and the second region remains unexposed.

Abstract: Methods for forming a memory cell are disclosed. A method includes forming a source-drain structure in a semiconductor substrate where the source-drain structure includes a rounded top surface and sidewall surfaces. An oxide layer is formed on the top and sidewall surfaces of the source-drain structure. The thickness of the portion of the oxide layer that is formed on the top surface of the source-drain structure is greater than the thickness of the portion of the oxide layer that is formed on the sidewall surfaces of the source-drain structure.

Abstract: A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.

Abstract: A method for fabricating a memory device with U-shaped trap layers over rounded active region corners is disclosed. In the present invention, an STI process is performed before the charge-trapping layer is formed. Immediately after the STI process, the sharp corners of the active regions are exposed, making them available for rounding. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, a bottom oxide layer, nitride layer, and sacrificial top oxide layer are formed. An organic bottom antireflective coating applied to the charge trapping layer is planarized. Now the organic bottom antireflective coating, sacrificial top oxide layer, and nitride layer are etched, without etching the sacrificial top oxide layer and nitride layer over the active regions. After the etching the charge trapping layer has a cross-sectional U-shape appearance.

Abstract: Methods for fabricating a FIN structure with a semicircular top surface and rounded top surface corners and edges are disclosed. As a part of a disclosed method, a FIN structure is formed in a semiconductor substrate. The FIN structure includes a top surface having corners and edges. The FIN structure is annealed where the annealing causes the top surface to have a semicircular shape and the top surface corners and edges to be rounded.

Abstract: A method for programming a single bit nonvolatile memory cell integrated on a metal-dielectric-semiconductor technology chip. The memory cell comprises a semiconductor substrate including a source, a drain, and a channel in-between the source and the drain. The memory cell further comprises a control gate that comprises a gate electrode and a dielectric stack. The gate electrode is separated from the channel by the dielectric stack. Further, the dielectric stack comprises at least one charge storage dielectric layer. The method for programming the memory cell comprises applying electrical ground to the source, applying a first voltage having a first polarity to the drain, applying a second voltage of the first polarity to the control gate; and applying a third voltage having a second polarity opposite to the first polarity to the semiconductor substrate.

Abstract: A method for programming a single bit nonvolatile memory cell integrated on a metal-dielectric-semiconductor technology chip. The memory cell comprises a semiconductor substrate including a source, a drain, and a channel in-between the source and the drain. The memory cell further comprises a control gate that comprises a gate electrode and a dielectric stack. The gate electrode is separated from the channel by the dielectric stack. Further, the dielectric stack comprises at least one charge storage dielectric layer. The method for programming the memory cell comprises applying electrical ground to the source, applying a first voltage having a first polarity to the drain, applying a second voltage of the first polarity to the control gate; and applying a third voltage having a second polarity opposite to the first polarity to the semiconductor substrate.

Abstract: Apparatus for an electrically programmable and erasable memory device and methods for programming, erasing and reading the device. The device has a single transistor including a source, a drain, a control gate and a floating gate positioned between the control gate, the source and the drain, where the floating gate is capacitively coupled to the drain. At least one part of the floating gate is partly positioned between the control gate, the drain and the source, and the other part of the floating gate overlaps with the drain. Further, the single transistor of the device includes means for injecting hot electrons generated by the drain induced secondary impact ionization onto the floating gate. Additionally, the means are arranged to induce Fowler-Nordheim tunnelling of charges from the floating gate to the drain.