Abstract: A shift register includes cascade-connected stages, each of which includes a data latch and an output stage. In at least one embodiment, the latch has a single data input which, in use, receives a date signal from a preceding or succeeding stage. The output stage includes a first switch, which passes a clock signal to the stage output when the output stage is activated by the latch. The output stage also comprises a second switch, which passes the lower supply voltage to the stage output when the output stage is inactive.

Abstract: A static random-access memory (SRAM) cell which includes: a sampling switch and a feedback switch; and a first inverter and a second inverter connected in series whereby an output of the first inverter is connected to an input of the second inverter. An input of the first inverter is connected to a data input of the SRAM cell via the sampling switch, and to a data output of the SRAM cell independent of the feedback switch, an output of the second inverter is connected to the input of the first inverter via the feedback switch, and first and second clock inputs of the SRAM cell are configured to control the sampling switch and the feedback switch, respectively.

Abstract: A serial-to-parallel converter which includes n input latching elements; k intermediate latching elements, and n output latching elements configured to sample outputs of the k intermediate latching elements and a remaining (n?k) input latching elements of the n input latching elements, respectively, after the nth data of the n successive data has been sampled by the nth input latching element and before the kth data of a next n successive data in the serial input data stream has been sampled by the kth input latching element, wherein the n input latching elements and the k intermediate latching elements are transparent for one state of their clock input, and n and k are positive integers, where n>k.

Abstract: A serial-to-parallel converter which includes n input latching elements; k intermediate latching elements, and n output latching elements configured to sample outputs of the k intermediate latching elements and a remaining (n?k) input latching elements of the n input latching elements, respectively, after the nth data of the n successive data has been sampled by the nth input latching element and before the kth data of a next n successive data in the serial input data stream has been sampled by the kth input latching element, wherein the n input latching elements and the k intermediate latching elements are transparent for one state of their clock input, and n and k are positive integers, where n>k.

Abstract: A microfluidic device includes a plurality of array elements configured to manipulate one or more droplets of fluid on an array, each of the array elements including a top substrate electrode and a drive electrode between which the one or more droplets may be positioned, the top substrate electrode being formed on a top substrate, and the drive electrode being formed on a lower substrate; and active matrix drive circuitry arranged to provide drive signals to the top substrate and drive electrodes of the plurality of array elements to manipulate the one or more droplets among the plurality of array elements. With respect to one or more of the array elements the active matrix drive circuitry is configured to provide the drive signals to the top substrate and drive electrodes to selectively manipulate the one or more droplets within the array element both by Electro-wetting-on-Dielectric (EWOD) and by Dielectrophoresis (DEP).

Abstract: In one embodiment of the present invention, a drive circuit includes: a logic block connected between a source of a first voltage and a source of a second voltage, and a sampler including a plurality of sampling circuits. Each sampling circuit is for sampling, in use, an input data signal and outputting a voltage to a respective output. The drive circuit further includes a voltage booster having plurality of voltage boost circuits, each voltage boost circuit being associated with a respective one of the sampling circuits and, in use, generating a boosted voltage signal and providing the boosted voltage signal to the respective sampling circuit. Each voltage boost circuit is connected between the source of the first voltage and the source of the second voltage. The logic block may be, but is not limited to, a shift register.

Abstract: An active matrix electrowetting on dielectric (AM-EWOD) device which includes a plurality of array elements configured to manipulate one or more droplets of fluid on an array, each of the array elements including a corresponding array element circuit. Each array element circuit includes a top substrate electrode and a drive electrode between which the one or more droplets may be positioned; circuitry configured to write data to the corresponding array element by selectively applying to the drive electrode either: (i) a time-varying voltage waveform V1 of amplitude VB and period t0; or (ii) a time-varying voltage waveform V2, the logical inverse of V1, and applying to the top substrate electrode the time-varying voltage waveform V2+Voffset, where Voffset represents an offset voltage signal which may have AC and/or DC components and may equal zero.

Abstract: A static random-access memory (SRAM) cell which includes: a sampling switch and a feedback switch; and a first inverter and a second inverter connected in series whereby an output of the first inverter is connected to an input of the second inverter. An input of the first inverter is connected to a data input of the SRAM cell via the sampling switch, and to a data output of the SRAM cell independent of the feedback switch, an output of the second inverter is connected to the input of the first inverter via the feedback switch, and first and second clock inputs of the SRAM cell are configured to control the sampling switch and the feedback switch, respectively.

Abstract: A shift register includes cascade-connected stages, each of which includes a data latch and an output stage. In at least one embodiment, the latch has a single data input which, in use, receives a date signal from a preceding or succeeding stage. The output stage includes a first switch, which passes a clock signal to the stage output when the output stage is activated by the latch. The output stage also comprises a second switch, which passes the lower supply voltage to the stage output when the output stage is inactive.

Abstract: In one embodiment of the present invention, a shift register includes a plurality of stages which are activated in sequence. Each stage includes a logic circuit controlling first and second output circuits. The first output circuit includes a first switch in the form of a transistor, which connects an output of the stage to receive a pulse width control signal when the stage is active. A second switch in the form of a transistor connects the stage output to receive an inactive signal level when the stage is inactive. The second output circuit comprises a third switch in the form of a transistor, which connects a further output to receive an active signal level when the stage is active. A fourth switch in the form of a transistor connects the further output to receive an inactive signal level when the stage is inactive. The further output of each stage is connected to the logic circuit of at least one adjacent stage, such as a reset input of a preceding stage and/or a set input of a succeeding stage.

Abstract: In one embodiment of the present invention, a drive circuit includes: a logic block connected between a source of a first voltage and a source of a second voltage, and a sampler including a plurality of sampling circuits. Each sampling circuit is for sampling, in use, an input data signal and outputting a voltage to a respective output. The drive circuit further includes a voltage booster having plurality of voltage boost circuits, each voltage boost circuit being associated with a respective one of the sampling circuits and, in use, generating a boosted voltage signal and providing the boosted voltage signal to the respective sampling circuit. Each voltage boost circuit is connected between the source of the first voltage and the source of the second voltage. The logic block may be, but is not limited to, a shift register.

Abstract: The invention concerns 3-arylthio-propyl-amino-3,4-dihydro-2H-1,5-aryloxathiepin derivatives of general formula (I), wherein: R1 and R2, identical or different, represent a hydrogen atom, a fluorine atom or a chlorine atom, a hydroxy group, an alkyl, cyclopropyl, alkoxy, cyclopropoxy radical or when they occupy adjacent positions, form with the carbon atoms bearing them a carbon-containing cycle or an oxygen-containing heterocycle with five non-aromatic rings; R3 represents an alkyl radical, a hydroxy group or a methoxy radical; R4 represents a hydrogen atom or a methyl radical; and R5 and R6, identical or different represent a hydrogen atom, an alkyl, alkoxy, alkylthio, alkylamino radical, or the groups OR4 and R5 form with the carbons which bear them a non-aromatic heterocycle with five or six rings containing at least an oxygen atom; and their pharmaceutically acceptable additions salts

Abstract: The invention concerns compounds of formula (I) wherein: R1 and R2, identical or different, represent a saturated or unsaturated alkyl radical, branched or not and containing 1 to 7 carbon atoms; R3 to R8, identical or different, represent a hydrogen, an alkyl branched or not and containing 1 to 5 carbon atoms, an acyloxy, branched or not and containing 1 to 5 carbon atoms, a halogeno, nitro, hydroxy, acyl or alkoxy group containing 1 to 5 carbon atoms, a dialkylamino group containing 1 to 5 carbon atoms, a trifluoromethyl or trifluoro methoxyl group; Z represents an oxygen or sulphur atom or methylene; m represents an integer between 0 and 4 inclusively; n represents an integer between 2 and 7 inclusively; and their pure enantiomers and mixtures, the therapeutically acceptable mineral or organic salts of the compounds of formula (I) and their possible hydrates.

Abstract: The invention concerns compounds of formula (I) wherein: R1 and R2, identical or different, represent a saturated or unsaturated alkyl radical, branched or not and containing 1 to 7 carbon atoms; R3 to R8, identical or different, represent a hydrogen, an alkyl branched or not and containing 1 to 5 carbon atoms, an acyloxy, branched or not and containing 1 to 5 carbon atoms, a halogeno, nitro, hydroxy, acyl or alkoxy group containing 1 to 5 carbon atoms, a dialkylamino group containing 1 to 5 carbon atoms, a trifluoromethyl or trifluoro methoxyl group; Z represents an oxygen or sulphur atom or methylene; m represents an integer between 0 and 4 inclusively; n represents an integer between 2 and 7 inclusively; and their pure enantiomers and mixtures, the therapeutically acceptable mineral or organic salts of the compounds of formula (I) and their possible hydrates.

Abstract: The invention concerns novel substituted N-benzo(thia/oxa)zines-2-yl-1-arylalkyloxyalkyl-4-piperidinamine, their preparation and their therapeutic use. The invention concerns compounds of formula (1) wherein: X represents an oxygen or sulphur atom; Y represents either an alkylene radical, branched or not and containing 2 to 6 carbon atoms or a CH2—CH(OH)—CH2— radical.

Abstract: The present invention relates to new aromatic ethers derived from indole and having general formula (I) as well as to their preparation methods, pharmaceutical compositions containing them and their utilization as a medicament for the treatment of diseases linked to the dysfunction of the 5HT.sub.1 -like receptors.