Abstract: Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an undoped silicon film. If the semiconductor structure is a capacitor, the protrusions help to increase the capacitance of the capacitor. The semiconductor structure also includes a relatively smooth surface abutting the rough surface, wherein the relatively smooth surface is formed from a polycrystalline material.

Abstract: Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is fabricated by forming a texturizing underlayer and then depositing a conductive material thereover. In one embodiment of a method of forming the lower electrode, the texturizing layer is formed by depositing a polymeric material comprising a hydrocarbon block and a silicon-containing block, over the insulative layer of a container, and then subsequently converting the polymeric film to relief or porous nanostructures by exposure to UV radiation and ozone, resulting in a textured porous or relief silicon oxycarbide film. A conductive material is then deposited over the texturizing layer resulting in a lower electrode have an upper roughened surface.

Abstract: Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an undoped silicon film. If the semiconductor structure is a capacitor, the protrusions help to increase the capacitance of the capacitor. The semiconductor structure also includes a relatively smooth surface abutting the rough surface, wherein the relatively smooth surface is formed from a polycrystalline material.

Abstract: Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an undoped silicon film. If the semiconductor structure is a capacitor, the protrusions help to increase the capacitance of the capacitor. The semiconductor structure also includes a relatively smooth surface abutting the rough surface, wherein the relatively smooth surface is formed from a polycrystalline material.

Abstract: Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is fabricated by forming a texturizing underlayer and then depositing a conductive material thereover. In one embodiment of a method of forming the lower electrode, the texturizing layer is formed by depositing a polymeric material comprising a hydrocarbon block and a silicon-containing block, over the insulative layer of a container, and then subsequently converting the polymeric film to relief or porous nanostructures by exposure to UV radiation and ozone, resulting in a textured porous or relief silicon oxycarbide film. A conductive material is then deposited over the texturizing layer resulting in a lower electrode have an upper roughened surface.

Abstract: Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: A capacitor fabrication method may include forming a first capacitor electrode over a substrate, the first electrode having an inner surface area per unit area and an outer surface area per unit area that are both greater than an outer surface area per unit area of the substrate. A capacitor dielectric layer and a second capacitor electrode may be formed over the dielectric layer. The method may further include forming rugged polysilicon over the substrate, the first electrode being over the rugged polysilicon. Accordingly, the outer surface area of the first electrode can be at least 30% greater than the outer surface area of the substrate without the first electrode including polysilicon.

Abstract: The present invention provides an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor is provided in a trench in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. A first dielectric layer is deposited over the first conductor and insulating layer to a thickness at least greater than the thickness of a desired MRAM cell. The first dielectric layer is patterned and etched to form an opening over the first conductor for the cell shapes. The magnetic layers comprising the MRAM cell are consecutively formed within the cell shapes and the first dielectric layer.

Abstract: A deposition method includes forming a nucleation layer over a substrate, forming a layer of a first substance at least one monolayer thick chemisorbed on the nucleation layer, and forming a layer of a second substance at least one monolayer thick chemisorbed on the first substance. The chemisorption product of the first and second substance may include silicon and nitrogen. The nucleation layer may comprise silicon nitride. Further, a deposition method may include forming a first part of a nucleation layer on a first surface of a substrate and forming a second part of a nucleation layer on a second surface of the substrate. A deposition layer may be formed on the first and second parts of the nucleation layer substantially non-selectively on the first part of the nucleation layer compared to the second part. The first surface may be a surface of a borophosphosilicate glass layer. The second surface may be a surface of a rugged polysilicon layer.

Abstract: A deposition method includes forming a nucleation layer over a substrate, forming a layer of a first substance at least one monolayer thick chemisorbed on the nucleation layer, and forming a layer of a second substance at least one monolayer thick chemisorbed on the first substance. The chemisorption product of the first and second substance may include silicon and nitrogen. The nucleation layer may comprise silicon nitride. Further, a deposition method may include forming a first part of a nucleation layer on a first surface of a substrate and forming a second part of a nucleation layer on a second surface of the substrate. A deposition layer may be formed on the first and second parts of the nucleation layer substantially non-selectively on the first part of the nucleation layer compared to the second part. The first surface may be a surface of a borophosphosilicate glass layer. The second surface may be a surface of a rugged polysilicon layer.

Abstract: Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is fabricated by forming a texturizing underlayer and then depositing a conductive material thereover. In one embodiment of a method of forming the lower electrode, the texturizing layer is formed by depositing a polymeric material comprising a hydrocarbon block and a silicon-containing block, over the insulative layer of a container, and then subsequently converting the polymeric film to relief or porous nanostructures by exposure to UV radiation and ozone, resulting in a textured porous or relief silicon oxycarbide film. A conductive material is then deposited over the texturizing layer resulting in a lower electrode have an upper roughened surface.

Abstract: A capacitor fabrication method may include atomic layer depositing a conductive barrier layer to oxygen diffusion over the first electrode. A method may instead include chemisorbing a layer of a first precursor at least one monolayer thick over the first electrode and chemisorbing a layer of a second precursor at least one monolayer thick on the first precursor layer, a chemisorption product of the first and second precursor layers being comprised by a layer of a conductive barrier material. The barrier layer may be sufficiently thick and dense to reduce oxidation of the first electrode by oxygen diffusion from over the barrier layer. An alternative method may include forming a first capacitor electrode over a substrate, the first electrode having an inner surface area per unit area and an outer surface area per unit area that are both greater than an outer surface area per unit area of the substrate. A capacitor dielectric layer and a second capacitor electrode may be formed over the dielectric layer.

Abstract: The present invention provides a method of forming an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor is provided in a trench in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. Then, a first dielectric layer is deposited over the first conductor and insulating layer to a thickness at least greater than the thickness of a desired MRAM cell. The first dielectric layer is then patterned and etched to form an opening over the first conductor for the cell shapes. Then, the magnetic layers comprising the MRAM cell are consecutively formed within the cell shapes and the first dielectric layer.

Abstract: Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is fabricated by forming a texturizing underlayer and then depositing a conductive material thereover. In one embodiment of a method of forming the lower electrode, the texturizing layer is formed by depositing a polymeric material comprising a hydrocarbon block and a silicon-containing block, over the insulative layer of a container, and then subsequently converting the polymeric film to relief or porous nanostructures by exposure to UV radiation and ozone, resulting in a textured porous or relief silicon oxycarbide film. A conductive material is then deposited over the texturizing layer resulting in a lower electrode have an upper roughened surface.

Abstract: Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is fabricated by forming a texturizing underlayer and then depositing a conductive material thereover. In one embodiment of a method of forming the lower electrode, the texturizing layer is formed by depositing a polymeric material comprising a hydrocarbon block and a silicon-containing block, over the insulative layer of a container, and then subsequently converting the polymeric film to relief or porous nanostructures by exposure to UV radiation and ozone, resulting in a textured porous or relief silicon oxycarbide film. A conductive material is then deposited over the texturizing layer resulting in a lower electrode have an upper roughened surface.

Abstract: Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an undoped silicon film. If the semiconductor structure is a capacitor, the protrusions help to increase the capacitance of the capacitor. The semiconductor structure also includes a relatively smooth surface abutting the rough surface, wherein the relatively smooth surface is formed from a polycrystalline material.

Abstract: The present invention provides a method of forming an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor is provided in a trench in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. Then, a first dielectric layer is deposited over the first conductor and insulating layer to a thickness at least greater than the thickness of a desired MRAM cell. The first dielectric layer is then patterned and etched to form an opening over the first conductor for the cell shapes. Then, the magnetic layers comprising the MRAM cell are consecutively formed within the cell shapes and the first dielectric layer.

Abstract: A capacitor fabrication method may include atomic layer depositing a conductive barrier layer to oxygen diffusion over the first electrode. A method may instead include chemisorbing a layer of a first precursor at least one monolayer thick over the first electrode and chemisorbing a layer of a second precursor at least one monolayer thick on the first precursor layer, a chemisorption product of the first and second precursor layers being comprised by a layer of a conductive barrier material. The barrier layer may be sufficiently thick and dense to reduce oxidation of the first electrode by oxygen diffusion from over the barrier layer. An alternative method may include forming a first capacitor electrode over a substrate, the first electrode having an inner surface area per unit area and an outer surface area per unit area that are both greater than an outer surface area per unit area of the substrate. A capacitor dielectric layer and a second capacitor electrode may be formed over the dielectric layer.