Abstract: Aspects of the invention include monitoring frames of bits received at a receiver for transmission errors. At least one of the received frames of bits includes cyclic redundancy code (CRC) bits for a first type of CRC check. It is determined whether a change in transmission errors has occurred in the received frames by performing the first type of CRC check based at least in part on the received CRC bits and payload bits in the received frames. A change from the first type of CRC check to a second type of CRC check is initiated at the receiver based at least in part on determining that a change in transmission errors has occurred. The change is synchronized between the receiver and the transmitter, and performed in parallel with functional operations performed by the receiver.

Abstract: Aspects of the invention include using a cyclic redundancy code (CRC) multiple-input signature register (MISR) for early warning and fail detection. Received bits are monitored at a receiver for transmission errors. The monitoring includes receiving frames of bits that are a subset of frames of bits used by the transmitter to generate a multi-frame CRC. At least one of the received frames of bits includes payload bits and a source single check bit not included in the multi-frame CRC. It is determined whether a transmission error has occurred in the received frames of bits. The determining includes generating a calculated single check bit based at least in part on bits in the received frames of bits, and comparing the received source single check bit to the calculated single check bit. An error indication is transmitted to the transmitter if they don't match.

Abstract: A host divides a dataset into stripes and sends the stripes to respective data chips of a distributed memory buffer system, where the data chips buffer the respective slices. Each data chip can buffer stripes from multiple datasets. Through the use of: (i) error detection methods; (ii) tagging the stripes for identification; and (iii) acknowledgement responses from the data chips, the host keeps track of the status of each slice at the data chips. If errors are detected for a given stripe, the host resends the stripe in the next store cycle, concurrently with stripes for the next dataset. Once all stripes have been received error-free across all the data chips, the host issues a store command which triggers the data chips to move the respective stripes from buffer to memory.

Abstract: A system for memory management includes an incoming memory data strobe connecting a memory data interface, and a clock distribution network. The clock distribution network includes an internal clock aligned to the incoming memory data strobe. The system also includes an asynchronous clock domain that is asynchronous with the clock distribution network; and a strobe select circuit configured to align to the incoming memory data strobe. The clock distribution network is configured to propagate read data with reduced latency from the memory data interface to a second interface.

Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.

Abstract: A calibration controller tests an electronic circuit to iteratively perform, concurrently, a write test with a write delay, a read test with a read delay, and a CAC test with a CAC delay on an electronic circuit over a range of a plurality of conditions while simultaneously adjusting the write delay, the read delay, and the CAC delay for each iteration until a read edge, a write edge, and a CAC edge are detected for each condition of the range of the plurality of types of conditions. The calibration controller identifies, from the read edge, the write edge, and the CAC edge detected for each condition of the range of the plurality of types of conditions, a calibrated delay value for each of the write delay, the read delay, and the CAC delay for the range plurality of types of conditions to adjust the signal delays for each of write data, read data, and CAC data signal to arrive for latching within a separate valid window of time.

Abstract: A calibration controller tests an electronic circuit to identify an initial read check with a read delay, an initial write check with a write delay, and an initial command, address, control (CAC) check with a CAC delay indicated as passing. Responsive to the initial read check, the initial write check, and the initial CAC check indicated as passing, for each setting of the read delay, the write delay, and the CAC delay, the calibration controller iteratively performs concurrently, a write test with the write delay, a read test with the read delay, and a CAC test with the CAC delay on the electronic circuit over the range of conditions while simultaneously adjusting the write delay, the read delay, and the CAC delay for each iteration until one or more of a read edge, a write edge, and a CAC edge are detected.

Abstract: A calibration controller tests an electronic circuit to identify an initial read check with a read delay, an initial write check with a write delay, and an initial command, address, control (CAC) check with a CAC delay indicated as passing. Responsive to the initial read check, the initial write check, and the initial CAC check indicated as passing, for each setting of the read delay, the write delay, and the CAC delay, the calibration controller iteratively performs concurrently, a write test with the write delay, a read test with the read delay, and a CAC test with the CAC delay on the electronic circuit over the range of conditions while simultaneously adjusting the write delay, the read delay, and the CAC delay for each iteration until one or more of a read edge, a write edge, and a CAC edge are detected.

Abstract: A host divides a dataset into stripes and sends the stripes to respective data chips of a distributed memory buffer system, where the data chips buffer the respective slices. Each data chip can buffer stripes from multiple datasets. Through the use of: (i) error detection methods; (ii) tagging the stripes for identification; and (iii) acknowledgement responses from the data chips, the host keeps track of the status of each slice at the data chips. If errors are detected for a given stripe, the host resends the stripe in the next store cycle, concurrently with stripes for the next dataset. Once all stripes have been received error-free across all the data chips, the host issues a store command which triggers the data chips to move the respective stripes from buffer to memory.

Abstract: To calibrate an electronic circuit, a calibration controller tests the electronic circuit with an initial separate read check allowing for a read delay and with an initial separate write check allowing for a write delay. The calibration controller, responsive to passing the initial read check and the initial write check, for each condition of a range of conditions, iteratively performs a write test with the write delay concurrent with a read test with the read delay on the electronic circuit over the range of conditions while simultaneously adjusting the write delay and adjusting the read delay for each iteration until one or more of a read edge and a write edge are detected.

Abstract: A method for fabricating a circuit comprises identifying a target on the circuit with a transitional sensitivity, determining a test pattern that stresses the target, generating a verification model at the hierarchy of the target, creating a pattern and translating the pattern into a verification assertion, running the verification with the translated pattern, determining whether the verification assertion is a possible verification assertion following the running of the verification, obtaining a state of source laches and pin inputs responsive to determining that the formal verification assertion is a possible verification assertion following the running of the formal verification, translating the formal verification assertion into a coverage event, running a simulation with the coverage event, determining whether the coverage event occurred, and creating a manufacturing test responsive to determining that the coverage event occurred.

Abstract: A method for fabricating a circuit comprises identifying a target on the circuit with a transitional sensitivity, determining a test pattern that stresses the target, generating a verification model at the hierarchy of the target, creating a pattern and translating the pattern into a verification assertion, running the verification with the translated pattern, determining whether the verification assertion is a possible verification assertion following the running of the verification, obtaining a state of source laches and pin inputs responsive to determining that the formal verification assertion is a possible verification assertion following the running of the formal verification, translating the formal verification assertion into a coverage event, running a simulation with the coverage event, determining whether the coverage event occurred, and creating a manufacturing test responsive to determining that the coverage event occurred.

Abstract: A method for fabricating a circuit comprises identifying a target on the circuit with a transitional sensitivity, determining a test pattern that stresses the target, generating a verification model at the hierarchy of the target, creating a pattern and translating the pattern into a verification assertion, running the verification with the translated pattern, determining whether the verification assertion is a possible verification assertion following the running of the verification, obtaining a state of source latches and pin inputs responsive to determining that the formal verification assertion is a possible verification assertion following the running of the formal verification, translating the formal verification assertion into a coverage event, running a simulation with the coverage event, determining whether the coverage event occurred, and creating a manufacturing test responsive to determining that the coverage event occurred.

Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.

Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.

Abstract: A method for fabricating a circuit comprises identifying a target on the circuit with a transitional sensitivity, determining a test pattern that stresses the target, generating a verification model at the hierarchy of the target, creating a pattern and translating the pattern into a verification assertion, running the verification with the translated pattern, determining whether the verification assertion is a possible verification assertion following the running of the verification, obtaining a state of source laches and pin inputs responsive to determining that the formal verification assertion is a possible verification assertion following the running of the formal verification, translating the formal verification assertion into a coverage event, running a simulation with the coverage event, determining whether the coverage event occurred, and creating a manufacturing test responsive to determining that the coverage event occurred.

Abstract: To calibrate an electronic circuit, a calibration controller tests the electronic circuit with an initial separate read check allowing for a read delay and with an initial separate write check allowing for a write delay. The calibration controller, responsive to passing the initial read check and the initial write check, for each condition of a range of conditions, iteratively performs a write test with the write delay concurrent with a read test with the read delay on the electronic circuit over the range of conditions while simultaneously adjusting the write delay and adjusting the read delay for each iteration until one or more of a read edge and a write edge are detected.

Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A reference voltage (Vref) calibration mechanism reduces the time and resources for calibration by reducing the number of tests needed to sufficiently determine the boundaries of the data eye of the memory device by using a combination of small steps and small steps to find a preferred reference voltage. In one example, the Vref calibration mechanism uses small steps of the reference voltage in a first range above a nominal reference voltage to find a maximum eye width then uses small steps to more precisely find the maximum eye width. If a maximum reference voltage is found in the first range then the second range below the nominal reference voltage does not need to be tested thereby saving additional time and resources.

Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A reference voltage (Vref) calibration mechanism reduces the time and resources for calibration by reducing the number of tests needed to sufficiently determine the boundaries of the data eye of the memory device by using a combination of small steps and small steps to find a preferred reference voltage. In one example, the Vref calibration mechanism uses small steps of the reference voltage in a first range above a nominal reference voltage to find a maximum eye width then uses small steps to more precisely find the maximum eye width. If a maximum reference voltage is found in the first range then the second range below the nominal reference voltage does not need to be tested thereby saving additional time and resources.

Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.