Abstract: The present invention provides a system and method for controlling data entries in a hierarchical buffer system. The system includes an integrated circuit device with a memory core, a high speed upstream data bus, and a plurality of 1st tier buffers that receive data from the memory. The system further includes a 2nd tier transfer buffer spanning a plurality of asynchronous timing domains that delivers the data onto the upstream data bus to minimize gaps in a data transfer. The method includes managing the buffers to allow data to flow from a plurality of 1st tier buffers through a 2nd tier transfer buffer, and delivering the data onto a high speed data bus with pre-determined timing in a manner which minimizes latency to the extent that the returning read data beats are always transmitted contiguously with no intervening gaps.

Abstract: The present invention provides a system and method for controlling data entries in a hierarchical buffer system. The system includes an integrated circuit device comprising: a memory core, a shared data bus, and a plurality of 1st tier buffers that receive data from the memory. The system further includes a 2nd tier transfer buffer that delivers the data onto the shared data bus with pre-determined timing. The present invention can also be viewed as providing methods for controlling moving data entries in a hierarchical buffer system. The method includes managing the buffers to allow data to flow from a plurality of 1st tier buffers through a 2nd tier transfer buffer, and delivering the data onto a shared data bus with pre-determined timing.

Abstract: Disclosed is a software entity for constructing a Hybrid Cycle Simulation model comprising Compiled Data Units (CDUs) for use in design verification. The simulation model may contain a plurality of 1-cycle CDUs, optimized for simulation throughput, and 2-cycle CDUs, optimized for simulation accuracy, or a mixture thereof. Utilizing a netlist tool extracting hierarchical design source components for use, the construction checks that all inputs and outputs of any hierarchical design source components bind, and employs Object Traversal Directives for incorporating the selected CDUs into the simulation model. A data management method is used for tracking the validity of the components in the model. Additionally, a software entity (FACDDR) permits high bandwidth simulation of design components normally requiring cycle accurate simulation.

Abstract: A memory hub device with test logic is configured to communicate with memory devices via multiple hub device ports, and is also configured to communicate on one or more busses in an upstream and downstream direction. The test logic includes a built-in self test apparatus providing logic to simultaneously and independently test the memory devices interfaced to one or more of the hub device ports using read and write data patterns. The test logic also includes configuration registers to hold fault and diagnostic information, and to initiate one or more tests. The memory hub device can further include command collision detection logic, a trace array, buffer transmit mode logic, trigger logic, clock adjustment logic, transparent mode logic, and a configured command sequencer, as well as additional features.

Abstract: Gating rules for a device design containing microelectronic devices are tested using formal verification. Testbench design code is generated for a device design from a design source containing hardware design language code. A formal verification process on the testbench device code determines whether the devices within the device design will be stable or unstable under a gating condition. If the test shows a design is unstable under the gating condition; it is indicated that a hardware design fix for the device design is required. If not, the test ends.

Abstract: A double data rate elastic interface in which programmable latch stages provide an elastic delay, preferably on the driving side of the elastic interface. However, the invention is not limited to the driver side/chip, it can be implemented in the receiver side/chip as well. However, since the receiver side of an elastic interface already has complicated logic, the invention will be usually implemented on the driving side. The programmable latch stages on the driving chip side of the interface, can often operate at the local clock frequency (the same frequency as the elastic interface bus clock frequency), which in turn is half of the double data rate at which the receiving latch stages operate, thereby decreasing the logic and storage resources in the interface receivers. The programmable latch stages can also be used in the case that the local clock frequency is twice the elastic interface bus clock frequency.

Abstract: A memory hub device with test logic is configured to communicate with memory devices via multiple hub device ports, and is also configured to communicate on one or more busses in an upstream and downstream direction. The test logic includes a built-in self test apparatus providing logic to simultaneously and independently test the memory devices interfaced to one or more of the hub device ports using read and write data patterns. The test logic also includes configuration registers to hold fault and diagnostic information, and to initiate one or more tests. The memory hub device can further include command collision detection logic, a trace array, buffer transmit mode logic, trigger logic, clock adjustment logic, transparent mode logic, and a configured command sequencer, as well as additional features.

Abstract: Design Data Management uses one copy of common data sets along with a plurality of instances, while continuing to utilize the existing design databases and existing CAD tools. Allowing a minimum amount of user intervention to create and maintain the common data set, Design Data Management employs replicating common data sets into one or more clone data sets. The method preferred provides for replicating and synchronizing one or more data sets with a master data set, comprises providing data design management of a master data set and at least one clone data set, and copying a master physical design data set into one or more physical instances to enable customization of said one or more physical instances. The master data set describes at least one of: a design component, a circuit macro, and a circuit entity, and comprises logical data sets, and it comprise physical design data sets.

Abstract: The concept of applying fencing logic to Built-In Self Test (BIST) hardware structures for the purpose of segregating defective circuitry and utilizing the remaining good circuitry is a well known practice in the chip design industry. Described herein is a method for verifying that any particular implementation of partial fencing logic actually provides the desired behavior of blocking down-stream impact of all signals from fenced interfaces, and also ensuring that the partial fencing does not inadvertently preclude any common logic from being fully tested.

Abstract: Systems and methods for providing a variable frame format protocol in a cascade interconnected memory system. The systems include a memory hub device that utilizes a first bus interface to communicate on a high-speed bus. The hub device also includes frame decode logic for translating variable format frames received via the first bus interface into memory device commands and data. The translating includes identifying write data headers and associated write data for self-registering write to data buffer commands.

Abstract: Gating rules for a device design containing microelectronic devices are tested using formal verification. Testbench design code is generated for a device design from a design source containing hardware design language code. A formal verification process on the testbench device code determines whether the devices within the device design will be stable or unstable under a gating condition. If the test shows a design is unstable under the gating condition; it is indicated that a hardware design fix for the device design is required. If not, the test ends.

Abstract: Disclosed is a software entity for constructing a Hybrid Cycle Simulation model comprising Compiled Data Units (CDUs) for use in design verification. The simulation model may contain a plurality of 1-cycle CDUs, optimized for simulation throughput, and 2-cycle CDUs, optimized for simulation accuracy, or a mixture thereof. Utilizing a netlist tool extracting hierarchical design source components for use, the construction checks that all inputs and outputs of any hierarchical design source components bind, and employs Object Traversal Directives for incorporating the selected CDUs into the simulation model. A data management method is used for tracking the validity of the components in the model. Additionally, a software entity (FACDDR) permits high bandwidth simulation of design components normally requiring cycle accurate simulation.

Abstract: Disclosed is a method for constructing a Hybrid Cycle Simulation model comprising Compiled Data Units (CDUs) for use in design verification. The simulation model may contain a plurality of 1-cycle CDUs, optimized for simulation throughput, and 2-cycle CDUs, optimized for simulation accuracy, or a mixture thereof. Utilizing a netlist tool extracting hierarchical design source components for use, the construction checks that all inputs and outputs of any hierarchical design source components bind, and employs Object Traversal Directives for incorporating the selected CDUs into the simulation model. A data management method is used for tracking the validity of the components in the model. Additionally, a software entity (FACDDR) permits high bandwidth simulation of design components normally requiring cycle accurate simulation.

Abstract: The concept of applying fencing logic to Built-In Self Test (BIST) hardware structures for the purpose of segregating defective circuitry and utilizing the remaining good circuitry is a well known practice in the chip design industry. Described herein is a method for verifying that any particular implementation of partial fencing logic actually provides the desired behavior of blocking down-stream impact of all signals from fenced interfaces, and also ensuring that the partial fencing does not inadvertently preclude any common logic from being fully tested.

Abstract: Automated verification methodology parsing scripts auto generate testbench hardware design language, such as VHDL or Verilog, from the design source VHDL or Verilog. A formal verification model is then built comprising the testbench VHDL and the design under test. The resulting design verification tool then provides proofs and counterexamples for all of the rules, e.g., auto-generated rules, in the testbench.

Abstract: A method for processing data in a computer system using two main concepts for addressing this situation, from which numerous other implementations is achieved using a first and second main concept. The first is a method of managing a common data path among a plethora of facilities with a decentralized distributed management scheme. The second concept is a method for managing a shared data buffer or group of buffers between multitudes of facilities. By employing the concepts discussed in this invention, one can contemplate a complex dataflow consisting of a multiplicity of resources and data paths, whereby virtually any combination of sharing is possible. A single data path can be shared among multiple sources or sinks.

Abstract: Design Data Management uses one copy of common data sets along with a plurality of instances, while continuing to utilize the existing design databases and existing CAD tools. Allowing a minimum amount of user intervention to create and maintain the common data set, Design Data Management employs replicating common data sets into one or more clone data sets. The method preferred provides for replicating and synchronizing one or more data sets with a master data set, comprises providing data design management of a master data set and at least one clone data set, and copying a master physical design data set into one or more physical instances to enable customization of said one or more physical instances. The master data set describes at least one of: a design component, a circuit macro, and a circuit entity, and comprises logical data sets, and it comprise physical design data sets.

Abstract: As described herein the automated verification methodology parsing scripts auto generate test bench hardware design langaue, such as VHDL or Verilog, from the design source VHDL or Verilog. A formal verification model is then built comprising the testbench VHDL and the design under test. The resulting design verification tool then provides proofs and counterexamples for all of the rules, e.g., auto-generated rules, in the test bench.

Abstract: A double data rate elastic interface in which programmable latch stages provide an elastic delay, preferably on the driving side of the elastic interface. However, the invention is not limited to the driver side/chip, it can be implemented in the receiver side/chip as well. However, since the receiver side of an elastic interface already has complicated logic, the invention will be usually implemented on the driving side. The programmable latch stages on the driving chip side of the interface, can often operate at the local clock frequency (the same frequency as the elastic interface bus clock frequency), which in turn is half of the double data rate at which the receiving latch stages operate, thereby decreasing the logic and storage resources in the interface receivers. The programmable latch stages can also be used in the case that the local clock frequency is twice the elastic interface bus clock frequency.

Abstract: Disclosed is a method for constructing a Hybrid Cycle Simulation model comprising Compiled Data Units (CDUs) for use in design verification. The simulation model may contain a plurality of 1-cycle CDUs, optimized for simulation throughput, and 2-cycle CDUs, optimized for simulation accuracy, or a mixture thereof. Utilizing a netlist tool extracting hierarchical design source components for use, the contruction checks that all inputs and outputs of any hierarchical design source components bind, and employs Object Traversal Directives for incorporating the selected CDUs into the simulation model. A data management method is used for tracking the validity of the components in the model. Additionally, a software entity (FACDDR) permits high bandwidth simulation of design components normally requiring cycle accurate simulation.